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Date: Fri, 22 Mar 2024 15:23:21 +0000
From: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To: neil.armstrong@...aro.org, Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konrad.dybcio@...aro.org>,
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
 Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
 Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
 linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: usb: qcom,pmic-typec: drop port
 description

On 22/03/2024 15:09, neil.armstrong@...aro.org wrote:
>> TBH I think we should drop this HS, SS stuff from the connector 
>> definition - there's nothing to say in a h/w definition anywhere HS 
>> must be a port or indeed SS - not all hardware knows or cares about 
>> different HS/SS signalling.
> 
> It matches the USB-C connector electrical characteristics, which by spec 
> has, at least:
> - High-Speed USB Line
> - up to 4 differential high-speed lanes that can be switched to DP, USB2 
> or PCIe
> - SideBand line (SBU)
> 
> And those 3 components can be handled by 3 different HW in the SoC, so 
> each one has a dedicated port.
> 
> Remember DT describes the HW, not the SW implementation.
> 
> Neil

Yes, you're right about that.

I suppose

1. Orientation switches should be defined as coming from a port on the
    connector associated with the CC pins.
    port@3:
    orientation-switch port name goes here

2. Data-role switches...
    Again the CC pins

https://community.silabs.com/s/article/what-s-the-role-of-cc-pin-in-type-c-solution?language=en_US

Maybe the right-thing-to-do is to add another port for the CC pins - 
which would still describe the hardware characteristics but would 
_accurately_ name the thing which does the data-role/orientation switching

CC1/CC2

Then we would not be abusing HS/SS/SBU for the port names - we'd be 
extending the connector definition but also naming the ports/endpoints 
appropriately associated with the data over the hw

---
bod

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