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Message-Id: <1711340191-69588-2-git-send-email-sugar.zhang@rock-chips.com>
Date: Mon, 25 Mar 2024 12:16:30 +0800
From: Sugar Zhang <sugar.zhang@...k-chips.com>
To: heiko@...ech.de
Cc: linux-rockchip@...ts.infradead.org,
Sugar Zhang <sugar.zhang@...k-chips.com>,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk input / output switch
This patch add support switch for clk-bidirection which located
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
and these config maybe located in many pieces of GRF,
which hard to addressed in one single clk driver. so, we add
this simple helper driver to address this situation.
In order to simplify implement and usage, and also for safety
clk usage (avoid high freq glitch), we set all clk out as disabled
(which means Input default for clk-bidrection) in the pre-stage,
such boot-loader or init by HW default. And then set a safety freq
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
in drivers.
e.g.
1. mclk{out,in}_sai0 define:
mclkin_sai0: mclkin-sai0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12288000>;
clock-output-names = "mclk_sai0_from_io";
};
mclkout_sai0: mclkout-sai0@...40070 {
compatible = "rockchip,clk-out";
reg = <0 0xff040070 0 0x4>;
clocks = <&cru MCLK_SAI0_OUT2IO>;
#clock-cells = <0>;
clock-output-names = "mclk_sai0_to_io";
rockchip,bit-shift = <4>;
//example with PD if reg access needed
power-domains = <&power RK3562_PD_VO>;
};
Note:
clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:
drivers/clk/rockchip/clk-rk3562.c:
PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
2. mclkout_sai0 usage:
&ext_codec {
clocks = <&mclkout_sai0>;
clock-names = "mclk";
assigned-clocks = <&mclkout_sai0>;
assigned-clock-rates = <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};
clk_summary on sai0 work:
cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
clk_sai0_src 1 1 0 1188000000 0 0 50000
clk_sai0_frac 1 1 0 12288000 0 0 50000
clk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0_out2io 1 1 0 12288000 0 0 50000
mclk_sai0_to_io 1 1 0 12288000 0 0 50000
example with PD if reg access needed:
* PD status when mclk_sai0_to_io on:
cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
/device runtime status
----------------------------------------------------------------------
...
vo on
/devices/platform/clocks/ff040070.mclkout-sai0 active
...
* PD status when mclk_sai0_to_io off:
cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
/device runtime status
----------------------------------------------------------------------
...
vo off-0
/devices/platform/clocks/ff040070.mclkout-sai0 suspended
...
3. mclkin_sai0 usage:
please override freq of mclkin as the real external clkin, such as:
&mclkin_sai0 {
clock-frequency = <24576000>;
}
&ext_codec {
clocks = <&mclkin_sai0>;
clock-names = "mclk";
assigned-clocks = <&cru CLK_SAI0>;
assigned-clock-parents = <&mclkin_sai0>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0m0_mclk>;
};
clk_summary on sai0 work:
cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
mclk_sai0_from_io 1 1 0 12288000 0 0 50000
clk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0 1 1 0 12288000 0 0 50000
mclk_sai0_out2io 0 0 0 12288000 0 0 50000
mclk_sai0_to_io 0 0 0 12288000 0 0 50000
Signed-off-by: Sugar Zhang <sugar.zhang@...k-chips.com>
---
.../bindings/clock/rockchip,clk-out.yaml | 107 +++++++++++++++++++++
1 file changed, 107 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
new file mode 100644
index 0000000..6582605
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Clock Out Control Module Binding
+
+maintainers:
+ - Sugar Zhang <sugar.zhang@...k-chips.com>
+
+description: |
+ This add support switch for clk-bidirection which located
+ at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
+ and these config maybe located in many pieces of GRF,
+ which hard to addressed in one single clk driver. so, we add
+ this simple helper driver to address this situation.
+
+ In order to simplify implement and usage, and also for safety
+ clk usage (avoid high freq glitch), we set all clk out as disabled
+ (which means Input default for clk-bidrection) in the pre-stage,
+ such boot-loader or init by HW default. And then set a safety freq
+ before enable clk-out, such as "assign-clock-rates" or clk_set_rate
+ in drivers.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,clk-out
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+ description: parent clocks.
+
+ power-domains:
+ maxItems: 1
+
+ clock-output-names:
+ maxItems: 1
+
+ rockchip,bit-shift:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Defines the bit shift of clk out enable.
+
+ rockchip,bit-set-to-disable:
+ type: boolean
+ description: |
+ By default this clock sets the bit at bit-shift to enable the clock.
+ Setting this property does the opposite: setting the bit disable
+ the clock and clearing it enables the clock.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+ - clock-output-names
+ - rockchip,bit-shift
+
+additionalProperties: false
+
+examples:
+ # Clock Provider node:
+ - |
+ mclkin_sai0: mclkin-sai0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ clock-output-names = "mclk_sai0_from_io";
+ };
+
+ mclkout_sai0: mclkout-sai0@...40070 {
+ compatible = "rockchip,clk-out";
+ reg = <0 0xff040070 0 0x4>;
+ clocks = <&cru MCLK_SAI0_OUT2IO>;
+ #clock-cells = <0>;
+ clock-output-names = "mclk_sai0_to_io";
+ rockchip,bit-shift = <4>;
+ };
+
+ # Clock mclkout Consumer node:
+ - |
+ ext_codec {
+ clocks = <&mclkout_sai0>;
+ clock-names = "mclk";
+ assigned-clocks = <&mclkout_sai0>;
+ assigned-clock-rates = <12288000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0m0_mclk>;
+ };
+
+ # Clock mclkin Consumer node:
+ - |
+ ext_codec {
+ clocks = <&mclkin_sai0>;
+ clock-names = "mclk";
+ assigned-clocks = <&cru CLK_SAI0>;
+ assigned-clock-parents = <&mclkin_sai0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0m0_mclk>;
+ };
--
2.7.4
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