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Message-ID: <ZgGrRrH0mxoKl90n@xhacker>
Date: Tue, 26 Mar 2024 00:50:14 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/5] clocksource/drivers/timer-clint: Add T-Head C9xx
clint support
On Tue, Mar 26, 2024 at 12:40:21AM +0800, Jisheng Zhang wrote:
> The mtimecmp in T-Head C9xx clint only supports 32bit read/write,
> implement such support.
>
> Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> ---
> drivers/clocksource/timer-clint.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c
> index 4537c77e623c..71188732e8a3 100644
> --- a/drivers/clocksource/timer-clint.c
> +++ b/drivers/clocksource/timer-clint.c
> @@ -34,6 +34,7 @@ static unsigned int clint_ipi_irq;
> static u64 __iomem *clint_timer_cmp;
> static unsigned long clint_timer_freq;
> static unsigned int clint_timer_irq;
> +static bool is_c900_clint;
>
> #ifdef CONFIG_SMP
> static void clint_send_ipi(unsigned int cpu)
> @@ -88,6 +89,19 @@ static int clint_clock_next_event(unsigned long delta,
> return 0;
> }
>
> +static int c900_clint_clock_next_event(unsigned long delta,
> + struct clock_event_device *ce)
> +{
> + void __iomem *r = clint_timer_cmp +
> + cpuid_to_hartid_map(smp_processor_id());
> + u64 val = clint_get_cycles64() + delta;
> +
> + csr_set(CSR_IE, IE_TIE);
> + writel_relaxed(val, r);
> + writel_relaxed(val >> 32, r + 4);
> + return 0;
> +}
> +
> static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = {
> .name = "clint_clockevent",
> .features = CLOCK_EVT_FEAT_ONESHOT,
> @@ -99,6 +113,9 @@ static int clint_timer_starting_cpu(unsigned int cpu)
> {
> struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu);
>
> + if (is_c900_clint)
> + ce->set_next_event = c900_clint_clock_next_event;
> +
> ce->cpumask = cpumask_of(cpu);
> clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX);
>
> @@ -233,5 +250,12 @@ static int __init clint_timer_init_dt(struct device_node *np)
> return rc;
> }
>
> +static int __init c900_clint_timer_init_dt(struct device_node *np)
> +{
> + is_c900_clint = true;
> + return clint_timer_init_dt(np);
> +}
> +
> TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt);
> TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
> +TIMER_OF_DECLARE(clint_timer2, "thead,c900-clint", clint_timer_init_dt);
oops, this should be "c900_clint_timer_init_dt", will update in v2.
> --
> 2.43.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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