linux-kernel - [PATCH v2 2/2] phy: marvell: a3700-comphy: Fix hardcoded array size

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Message-ID: <20240325201254.54445-3-m.kobuk@ispras.ru>
Date: Mon, 25 Mar 2024 23:12:50 +0300
From: Mikhail Kobuk <m.kobuk@...ras.ru>
To: Miquel Raynal <miquel.raynal@...tlin.com>
Cc: Mikhail Kobuk <m.kobuk@...ras.ru>,
	Vinod Koul <vkoul@...nel.org>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Pali Rohár <pali@...nel.org>,
	Marek Behún <kabel@...nel.org>,
	linux-phy@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	lvc-project@...uxtesting.org,
	Alexey Khoroshilov <khoroshilov@...ras.ru>
Subject: [PATCH v2 2/2] phy: marvell: a3700-comphy: Fix hardcoded array size

Replace hardcoded 'gbe_phy_init' array size with defined value.

Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation")
Signed-off-by: Mikhail Kobuk <m.kobuk@...ras.ru>
---
 drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
index 68710ad1ad70..5d6dccfca1fb 100644
--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
@@ -43,6 +43,7 @@
 #define COMPHY_LANE_REG_DIRECT(reg)	(((reg) & 0x7FF) << 1)
 
 /* COMPHY registers */
+#define COMPHY_GBE_PHY_MAX_REGS	512
 #define COMPHY_POWER_PLL_CTRL		0x01
 #define PU_IVREF_BIT			BIT(15)
 #define PU_PLL_BIT			BIT(14)
@@ -296,7 +297,7 @@ static struct gbe_phy_init_data_fix gbe_phy_init_fix[] = {
 };
 
 /* 40M1G25 mode init data */
-static u16 gbe_phy_init[512] = {
+static u16 gbe_phy_init[COMPHY_GBE_PHY_MAX_REGS] = {
 	/* 0       1       2       3       4       5       6       7 */
 	/*-----------------------------------------------------------*/
 	/* 8       9       A       B       C       D       E       F */
@@ -603,7 +604,7 @@ static void comphy_gbe_phy_init(struct mvebu_a3700_comphy_lane *lane,
 	u16 val;
 
 	fix_idx = 0;
-	for (addr = 0; addr < 512; addr++) {
+	for (addr = 0; addr < COMPHY_GBE_PHY_MAX_REGS; addr++) {
 		/*
 		 * All PHY register values are defined in full for 3.125Gbps
 		 * SERDES speed. The values required for 1.25 Gbps are almost
-- 
2.44.0