linux-kernel - Re: [PATCH v2 2/2] arm64: dts: rockchip: Add VEPU121 to rk3588

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Date: Wed, 27 Mar 2024 18:45:04 +0100
From: Sebastian Reichel <sebastian.reichel@...labora.com>
To: Emmanuel Gil Peyrot <linkmauve@...kmauve.fr>
Cc: linux-kernel@...r.kernel.org, 
	Ezequiel Garcia <ezequiel@...guardiasur.com.ar>, Philipp Zabel <p.zabel@...gutronix.de>, 
	Mauro Carvalho Chehab <mchehab@...nel.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Heiko Stuebner <heiko@...ech.de>, Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>, 
	Robin Murphy <robin.murphy@....com>, Cristian Ciocaltea <cristian.ciocaltea@...labora.com>, 
	Dragan Simic <dsimic@...jaro.org>, Shreeya Patel <shreeya.patel@...labora.com>, 
	Chris Morgan <macromorgan@...mail.com>, Andy Yan <andy.yan@...k-chips.com>, 
	Nicolas Frattaroli <frattaroli.nicolas@...il.com>, linux-media@...r.kernel.org, linux-rockchip@...ts.infradead.org, 
	devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, iommu@...ts.linux.dev
Subject: Re: [PATCH v2 2/2] arm64: dts: rockchip: Add VEPU121 to rk3588

Hi,

On Wed, Mar 27, 2024 at 02:41:12PM +0100, Emmanuel Gil Peyrot wrote:
> The TRM (version 1.0 page 385) lists five VEPU121 cores, but only four
> interrupts are listed (on page 24), so I’ve only enabled four of them
> for now.
> 
> Signed-off-by: Emmanuel Gil Peyrot <linkmauve@...kmauve.fr>
> ---

Reviewed-by: Sebastian Reichel <sebastian.reichel@...labora.com>

-- Sebastian

>  arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 +++++++++++++++++++++++
>  1 file changed, 80 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> index 87b83c87bd55..510ed3db9d01 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -2488,6 +2488,86 @@ gpio4: gpio@...50000 {
>  		};
>  	};
>  
> +	jpeg_enc0: video-codec@...a0000 {
> +		compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
> +		reg = <0x0 0xfdba0000 0x0 0x800>;
> +		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&jpeg_enc0_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	jpeg_enc0_mmu: iommu@...a0800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdba0800 0x0 0x40>;
> +		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
> +	jpeg_enc1: video-codec@...a4000 {
> +		compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
> +		reg = <0x0 0xfdba4000 0x0 0x800>;
> +		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&jpeg_enc1_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	jpeg_enc1_mmu: iommu@...a4800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdba4800 0x0 0x40>;
> +		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
> +	jpeg_enc2: video-codec@...a8000 {
> +		compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
> +		reg = <0x0 0xfdba8000 0x0 0x800>;
> +		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&jpeg_enc2_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	jpeg_enc2_mmu: iommu@...a8800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdba8800 0x0 0x40>;
> +		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
> +	jpeg_enc3: video-codec@...ac000 {
> +		compatible = "rockchip,rk3588-vepu121", "rockchip,rk3568-vepu";
> +		reg = <0x0 0xfdbac000 0x0 0x800>;
> +		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> +		clock-names = "aclk", "hclk";
> +		iommus = <&jpeg_enc3_mmu>;
> +		power-domains = <&power RK3588_PD_VDPU>;
> +	};
> +
> +	jpeg_enc3_mmu: iommu@...ac800 {
> +		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
> +		reg = <0x0 0xfdbac800 0x0 0x40>;
> +		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
> +		clock-names = "aclk", "iface";
> +		power-domains = <&power RK3588_PD_VDPU>;
> +		#iommu-cells = <0>;
> +	};
> +
>  	av1d: video-codec@...70000 {
>  		compatible = "rockchip,rk3588-av1-vpu";
>  		reg = <0x0 0xfdc70000 0x0 0x800>;
> -- 
> 2.44.0
> 

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