linux-kernel - Re: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support

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Message-ID: <171156223562.3706464.15520740960365102234.robh@kernel.org>
Date: Wed, 27 Mar 2024 12:57:16 -0500
From: Rob Herring <robh@...nel.org>
To: Conor Dooley <conor@...nel.org>
Cc: Jamie Gibbons <jamie.gibbons@...rochip.com>,
	Bartosz Golaszewski <brgl@...ev.pl>, linux-kernel@...r.kernel.org,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Daire McNamara <daire.mcnamara@...rochip.com>,
	devicetree@...r.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	linux-pci@...r.kernel.org, Linus Walleij <linus.walleij@...aro.org>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Krzysztof Wilczyński <kw@...ux.com>,
	linux-gpio@...r.kernel.org,
	Valentina Fernandez <valentina.fernandezalanis@...rochip.com>,
	linux-riscv@...ts.infradead.org,
	Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support


On Wed, 27 Mar 2024 12:24:37 +0000, Conor Dooley wrote:
> From: Jamie Gibbons <jamie.gibbons@...rochip.com>
> 
> The GPIO controllers on PolarFire SoC were based on the "soft" IP
> CoreGPIO, but the inp/outp registers are at different offsets. Add
> compatible to allow for support of both sets of offsets. The soft
> core will not always have interrupts wired up, so only enforce them for
> the "hard" core on PolarFire SoC.
> 
> Signed-off-by: Jamie Gibbons <jamie.gibbons@...rochip.com>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  .../bindings/gpio/microchip,mpfs-gpio.yaml       | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 

Reviewed-by: Rob Herring <robh@...nel.org>