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Message-ID: <CA+V-a8vuCBzo_2gXsccFuQgzBhWQ7JznFcNsEq_K_6RyhRp_5A@mail.gmail.com>
Date: Wed, 27 Mar 2024 08:13:20 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Dan Carpenter <dan.carpenter@...aro.org>
Cc: Geert Uytterhoeven <geert+renesas@...der.be>, Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>,
linux-renesas-soc@...r.kernel.org, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [RFC PATCH 07/13] pinctrl: renesas: pinctrl-rzg2l: Validate power
registers for SD and ETH
Hi Dan,
Thank you for the review.
On Wed, Mar 27, 2024 at 7:58 AM Dan Carpenter <dan.carpenter@...aroorg> wrote:
>
> On Tue, Mar 26, 2024 at 10:28:38PM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist,
> > resulting in invalid register offsets. Ensure that the register offsets
> > are valid before any read/write operations are performed. If the power
> ^^^^^^^^^^^^
> > registers are not available, both SD and ETH will be set to -EINVAL.
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> Where does this happen? It doesn't seem to be a part of this patchset.
> -EINVAL seems weird here, but it's hard to judge without actually seeing
> it.
>
Good catch, in patch 13/13 it should be below instead of sd_ch and
eth_poc assigned to 0.
+static const struct rzg2l_hwcfg rzv2h_hwcfg = {
+ .regs = {
+ .pwpr = 0x3c04,
+ .sd_ch = -EINVAL,
+ .eth_poc = -EINVAL,
+ },
+};
Cheers,
Prabhakar
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