linux-kernel - [PATCH 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata

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Message-ID: <20240327103130.3651950-3-christoph.muellner@vrull.eu>
Date: Wed, 27 Mar 2024 11:31:30 +0100
From: Christoph Müllner <christoph.muellner@...ll.eu>
To: linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Philipp Tomsich <philipp.tomsich@...ll.eu>,
	Björn Töpel <bjorn@...nel.org>,
	Daniel Henrique Barboza <dbarboza@...tanamicro.com>,
	Heiko Stuebner <heiko@...ech.de>,
	Cooper Qu <cooper.qu@...ux.alibaba.com>,
	Zhiwei Liu <zhiwei_liu@...ux.alibaba.com>,
	Huang Tao <eric.huang@...ux.alibaba.com>,
	Alistair Francis <alistair.francis@....com>,
	Andrew Jones <ajones@...tanamicro.com>,
	Conor Dooley <conor@...nel.org>
Cc: Christoph Müllner <christoph.muellner@...ll.eu>
Subject: [PATCH 2/2] riscv: T-Head: Test availability bit before enabling MAEE errata

T-Head's MAEE mechanism (non-compatible equivalent of RVI's Svpbmt)
is currently assumed for all T-Head harts. However, QEMU recently
decided to drop acceptance of guests that write reserved bits in PTEs.
As MAEE uses reserved bits in PTEs and Linux applies the MAEE errata
for all T-Head harts, this broke the Linux startup on QEMU emulations
of the C906 emulation.

This patch attempts to address this issue by testing the MAEE bit
in TH_MXSTATUS CSR. As the TH_MXSTATUS CSR is only accessible in M-mode
this patch depends on M-mode firmware that handles this for us
transparently.

As this patch breaks Linux bootup on all C9xx machines with MAEE,
which don't have M-mode firmware that handles the access to the
TH_MXSTATUS CSR, this patch is marked as RFC.

Signed-off-by: Christoph Müllner <christoph.muellner@...ll.eu>
---
 arch/riscv/errata/thead/errata.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
index 8c8a8a4b0421..dd7bf6c62a35 100644
--- a/arch/riscv/errata/thead/errata.c
+++ b/arch/riscv/errata/thead/errata.c
@@ -19,6 +19,9 @@
 #include <asm/patch.h>
 #include <asm/vendorid_list.h>
 
+#define CSR_TH_MXSTATUS		0x7c0
+#define MXSTATUS_MAEE		_AC(0x200000, UL)
+
 static bool errata_probe_maee(unsigned int stage,
 			      unsigned long arch_id, unsigned long impid)
 {
@@ -28,11 +31,14 @@ static bool errata_probe_maee(unsigned int stage,
 	if (arch_id != 0 || impid != 0)
 		return false;
 
-	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT ||
-	    stage == RISCV_ALTERNATIVES_MODULE)
-		return true;
+	if (stage != RISCV_ALTERNATIVES_EARLY_BOOT &&
+	    stage != RISCV_ALTERNATIVES_MODULE)
+		return false;
 
-	return false;
+	if (!(csr_read(CSR_TH_MXSTATUS) & MXSTATUS_MAEE))
+		return false;
+
+	return true;
 }
 
 /*
-- 
2.44.0