linux-kernel - [PATCH v4 4/5] clk: qcom: apss-ipq-pll: constify clk_init

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Message-Id: <20240328-apss-ipq-pll-cleanup-v4-4-eddbf617f0c8@gmail.com>
Date: Thu, 28 Mar 2024 10:23:13 +0100
From: Gabor Juhos <j4g8y7@...il.com>
To: Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konrad.dybcio@...aro.org>, 
 Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, 
 Michael Turquette <mturquette@...libre.com>, 
 Stephen Boyd <sboyd@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, 
 linux-kernel@...r.kernel.org, Gabor Juhos <j4g8y7@...il.com>
Subject: [PATCH v4 4/5] clk: qcom: apss-ipq-pll: constify clk_init_data
 structures

The clk_init_data structures are never modified, so add const
qualifier to the ones where it is missing.

No functional changes.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@...aro.org>
Signed-off-by: Gabor Juhos <j4g8y7@...il.com>
---
Changes in v4:
 - no changes
 - Link to v3: https://lore.kernel.org/r/20240326-apss-ipq-pll-cleanup-v3-4-15c4aeeb14ac@gmail.com

Changes in v3:
 - rebase on top of v6.9-rc1
 - add Reviewed-by tags from Dmitry and Konrad
 - Link to v2: https://lore.kernel.org/r/20240321-apss-ipq-pll-cleanup-v2-5-201f3cf79fd4@gmail.com

Changes in v2:
 - no changes
 - Link to v1: https://lore.kernel.org/r/20240318-apss-ipq-pll-cleanup-v1-5-52f795429d5d@gmail.com
---
 drivers/clk/qcom/apss-ipq-pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index 191b87df51bb..1a6f4db25379 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -15,7 +15,7 @@ static struct clk_alpha_pll ipq_pll_huayra = {
 	.clkr = {
 		.enable_reg = 0x0,
 		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
+		.hw.init = &(const struct clk_init_data) {
 			.name = "a53pll",
 			.parent_data = &(const struct clk_parent_data) {
 				.fw_name = "xo",
@@ -55,7 +55,7 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = {
 	.clkr = {
 		.enable_reg = 0x0,
 		.enable_mask = BIT(0),
-		.hw.init = &(struct clk_init_data){
+		.hw.init = &(const struct clk_init_data) {
 			.name = "a53pll",
 			.parent_data = &(const struct clk_parent_data) {
 				.fw_name = "xo",

-- 
2.44.0