linux-kernel - Re: [PATCH v2 3/3] clk: samsung: gs101: propagate PERIC0 USI SPI clock rate

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Message-ID: <3b9d28405f01c7bc23075492dbb501ebde0edbfa.camel@linaro.org>
Date: Thu, 28 Mar 2024 11:25:53 +0000
From: André Draszik <andre.draszik@...aro.org>
To: Tudor Ambarus <tudor.ambarus@...aro.org>, peter.griffin@...aro.org, 
	krzysztof.kozlowski@...aro.org
Cc: alim.akhtar@...sung.com, linux-arm-kernel@...ts.infradead.org, 
 linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org, 
 willmcvicker@...gle.com, kernel-team@...roid.com, s.nawrocki@...sung.com, 
 cw00.choi@...sung.com, mturquette@...libre.com, sboyd@...nel.org, 
 semen.protsenko@...aro.org, linux-clk@...r.kernel.org,
 jaewon02.kim@...sung.com
Subject: Re: [PATCH v2 3/3] clk: samsung: gs101: propagate PERIC0 USI SPI
 clock rate

On Tue, 2024-03-26 at 17:28 +0000, Tudor Ambarus wrote:
> When SPI transfer is being prepared, the spi-s3c64xx driver will call
> clk_set_rate() to change the rate of SPI source clock (IPCLK). But IPCLK
> is a gate (leaf) clock, so it must propagate the rate change up the
> clock tree, so that corresponding MUX/DIV clocks can actually change
> their values. Add CLK_SET_RATE_PARENT flag to corresponding clocks for
> all USI instances in GS101 PERIC0: USI{1-8, 14}. This change involves the
> following clocks:
> 
> PERIC0 USI*:
> 
>     Clock                              Div range    MUX Selection
>     -------------------------------------------------------------------
>     gout_peric0_peric0_top0_ipclk_*    -            -
>     dout_peric0_usi*_usi               /1..16       -
>     mout_peric0_usi*_usi_user          -            {24.5 MHz, 400 MHz}
> 
> With input clock of 400 MHz this scheme provides the following IPCLK
> rate range, for each USI block:
> 
>     PERIC0 USI*:       1.5 MHz ... 400 MHz
> 
> Accounting for internal /4 divider in SPI blocks, and because the max
> SPI frequency is limited at 50 MHz, it gives us next SPI SCK rates:
> 
>     PERIC0 USI_SPI*:   384 KHz ... 49.9 MHz
> 
> Which shall be fine for the applications of the SPI bus.
> 
> Note that with this we allow the reparenting of the MUX_USIx clocks to
> OSCCLK. Each instance of the USI IP has its own MUX_USI clock, thus the
> reparenting of a MUX_USI clock corresponds to a single instance of the
> USI IP. The datasheet mentions OSCCLK just in the low-power mode
> context, but the downstream driver reparents too the MUX_USI clocks to
> OSCCLK. Follow the downstream driver and do the same.
> 
> Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0")
> Signed-off-by: Tudor Ambarus <tudor.ambarus@...aro.org>

Acked-by: André Draszik <andre.draszik@...aro.org>