linux-kernel - Re: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support

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Message-ID: <CAMRc=McSRZUfsUEQcmOs+xUnCKiTX+kEqtXmmXe71Jbh7nzsvw@mail.gmail.com>
Date: Fri, 29 Mar 2024 11:28:53 +0100
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Conor Dooley <conor@...nel.org>
Cc: linux-riscv@...ts.infradead.org, Conor Dooley <conor.dooley@...rochip.com>, 
	Daire McNamara <daire.mcnamara@...rochip.com>, Jamie Gibbons <jamie.gibbons@...rochip.com>, 
	Valentina Fernandez <valentina.fernandezalanis@...rochip.com>, 
	Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, 
	Lorenzo Pieralisi <lpieralisi@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>, 
	Bjorn Helgaas <bhelgaas@...gle.com>, linux-gpio@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-pci@...r.kernel.org
Subject: Re: [PATCH v1 2/5] dt-bindings: gpio: mpfs: add coreGPIO support

On Wed, Mar 27, 2024 at 1:25 PM Conor Dooley <conor@...nel.org> wrote:
>
> From: Jamie Gibbons <jamie.gibbons@...rochip.com>
>
> The GPIO controllers on PolarFire SoC were based on the "soft" IP
> CoreGPIO, but the inp/outp registers are at different offsets. Add
> compatible to allow for support of both sets of offsets. The soft
> core will not always have interrupts wired up, so only enforce them for
> the "hard" core on PolarFire SoC.
>
> Signed-off-by: Jamie Gibbons <jamie.gibbons@...rochip.com>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---

Applied, thanks!

Bart