| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <654826d6-5fd8-4876-a0a5-8738e14eb06e@linaro.org>
Date: Sun, 31 Mar 2024 10:24:44 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Sugar Zhang <sugar.zhang@...k-chips.com>, heiko@...ech.de
Cc: linux-rockchip@...ts.infradead.org, Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>, Rob Herring <robh@...nel.org>,
Stephen Boyd <sboyd@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 2/2] dt-bindings: clock: rockchip: Add support for clk
input / output switch
On 25/03/2024 05:16, Sugar Zhang wrote:
> This patch add support switch for clk-bidirection which located
Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
> at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> and these config maybe located in many pieces of GRF,
> which hard to addressed in one single clk driver. so, we add
> this simple helper driver to address this situation.
>
> In order to simplify implement and usage, and also for safety
> clk usage (avoid high freq glitch), we set all clk out as disabled
> (which means Input default for clk-bidrection) in the pre-stage,
> such boot-loader or init by HW default. And then set a safety freq
> before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> in drivers.
>
> e.g.
>
> 1. mclk{out,in}_sai0 define:
>
> mclkin_sai0: mclkin-sai0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <12288000>;
> clock-output-names = "mclk_sai0_from_io";
> };
>
> mclkout_sai0: mclkout-sai0@...40070 {
> compatible = "rockchip,clk-out";
> reg = <0 0xff040070 0 0x4>;
> clocks = <&cru MCLK_SAI0_OUT2IO>;
> #clock-cells = <0>;
> clock-output-names = "mclk_sai0_to_io";
> rockchip,bit-shift = <4>;
> //example with PD if reg access needed
> power-domains = <&power RK3562_PD_VO>;
> };
>
> Note:
>
> clock-output-names of mclkin_sai0 should equal to strings in drivers. such as:
>
> drivers/clk/rockchip/clk-rk3562.c:
> PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
>
> 2. mclkout_sai0 usage:
>
> &ext_codec {
> clocks = <&mclkout_sai0>;
> clock-names = "mclk";
> assigned-clocks = <&mclkout_sai0>;
> assigned-clock-rates = <12288000>;
> pinctrl-names = "default";
> pinctrl-0 = <&i2s0m0_mclk>;
> };
>
> clk_summary on sai0 work:
>
> cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
>
> clk_sai0_src 1 1 0 1188000000 0 0 50000
> clk_sai0_frac 1 1 0 12288000 0 0 50000
> clk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0_out2io 1 1 0 12288000 0 0 50000
> mclk_sai0_to_io 1 1 0 12288000 0 0 50000
>
> example with PD if reg access needed:
>
> * PD status when mclk_sai0_to_io on:
>
> cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
>
> domain status children
> /device runtime status
> ----------------------------------------------------------------------
> ...
>
> vo on
> /devices/platform/clocks/ff040070.mclkout-sai0 active
> ...
>
> * PD status when mclk_sai0_to_io off:
>
> cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
>
> domain status children
> /device runtime status
> ----------------------------------------------------------------------
> ...
>
> vo off-0
> /devices/platform/clocks/ff040070.mclkout-sai0 suspended
> ...
>
> 3. mclkin_sai0 usage:
>
> please override freq of mclkin as the real external clkin, such as:
>
> &mclkin_sai0 {
> clock-frequency = <24576000>;
> }
>
> &ext_codec {
> clocks = <&mclkin_sai0>;
> clock-names = "mclk";
> assigned-clocks = <&cru CLK_SAI0>;
> assigned-clock-parents = <&mclkin_sai0>;
> pinctrl-names = "default";
> pinctrl-0 = <&i2s0m0_mclk>;
> };
>
> clk_summary on sai0 work:
>
> cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"
>
> mclk_sai0_from_io 1 1 0 12288000 0 0 50000
> clk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0 1 1 0 12288000 0 0 50000
> mclk_sai0_out2io 0 0 0 12288000 0 0 50000
> mclk_sai0_to_io 0 0 0 12288000 0 0 50000
None of this long commit msg is a description of hardware. Please remove
all unnecessary information and instead describe the problem you are
solving or the hardware.
>
> Signed-off-by: Sugar Zhang <sugar.zhang@...k-chips.com>
> ---
>
> .../bindings/clock/rockchip,clk-out.yaml | 107 +++++++++++++++++++++
> 1 file changed, 107 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> new file mode 100644
> index 0000000..6582605
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip Clock Out Control Module Binding
It does not look like you tested the bindings, at least after quick
look. Please run `make dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.
> +
> +maintainers:
> + - Sugar Zhang <sugar.zhang@...k-chips.com>
> +
> +description: |
> + This add support switch for clk-bidirection which located
No, "this does not add". This is description of hardware, thus describe
hardware.
> + at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
> + and these config maybe located in many pieces of GRF,
> + which hard to addressed in one single clk driver. so, we add
> + this simple helper driver to address this situation.
Bindings are for hardware, not drivers. Rephrase EVERYTHING to focus on
hardware, not driver. Otherwise it looks like you wrote it for drivers,
which is a NAK.
> +
> + In order to simplify implement and usage, and also for safety
> + clk usage (avoid high freq glitch), we set all clk out as disabled
> + (which means Input default for clk-bidrection) in the pre-stage,
> + such boot-loader or init by HW default. And then set a safety freq
> + before enable clk-out, such as "assign-clock-rates" or clk_set_rate
> + in drivers.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,clk-out
Missing SoC compatible. See writing bindings.
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 1
> + description: parent clocks.
Drop useless description.
> +
> + power-domains:
> + maxItems: 1
> +
> + clock-output-names:
> + maxItems: 1
> +
> + rockchip,bit-shift:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Defines the bit shift of clk out enable.
No, this is deduced from compatible.
> +
> + rockchip,bit-set-to-disable:
> + type: boolean
> + description: |
> + By default this clock sets the bit at bit-shift to enable the clock.
> + Setting this property does the opposite: setting the bit disable
> + the clock and clearing it enables the clock.
No, this is deduced from compatible.
Binding looks really poor, like written for some debug driver.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - "#clock-cells"
> + - clock-output-names
> + - rockchip,bit-shift
> +
> +additionalProperties: false
> +
> +examples:
> + # Clock Provider node:
> + - |
> + mclkin_sai0: mclkin-sai0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <12288000>;
> + clock-output-names = "mclk_sai0_from_io";
> + };
Drop, unrelated.
> +
> + mclkout_sai0: mclkout-sai0@...40070 {
Node names should be generic. See also an explanation and list of
examples (not exhaustive) in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "rockchip,clk-out";
> + reg = <0 0xff040070 0 0x4>;
> + clocks = <&cru MCLK_SAI0_OUT2IO>;
> + #clock-cells = <0>;
> + clock-output-names = "mclk_sai0_to_io";
> + rockchip,bit-shift = <4>;
> + };
> +
> + # Clock mclkout Consumer node:
> + - |
> + ext_codec {
Drop, not related, incorrect name.
> + clocks = <&mclkout_sai0>;
> + clock-names = "mclk";
> + assigned-clocks = <&mclkout_sai0>;
> + assigned-clock-rates = <12288000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0m0_mclk>;
> + };
> +
> + # Clock mclkin Consumer node:
> + - |
> + ext_codec {
Drop.
Don't upstream poor quality downstream code, but fix it first to match
upstream style. Read carefully writing bindings and DTS coding style.
Best regards,
Krzysztof
Powered by blists - more mailing lists