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Message-ID: <ZgworgDAXXOpf3QV@pengutronix.de>
Date: Tue, 2 Apr 2024 17:47:58 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: Rob Herring <robh@...nel.org>
Cc: Kory Maincent <kory.maincent@...tlin.com>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Jonathan Corbet <corbet@....net>,
Luis Chamberlain <mcgrof@...nel.org>,
Russ Weight <russ.weight@...ux.dev>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Mark Brown <broonie@...nel.org>,
Frank Rowand <frowand.list@...il.com>, Andrew Lunn <andrew@...n.ch>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, devicetree@...r.kernel.org,
Dent Project <dentproject@...uxfoundation.org>
Subject: Re: [PATCH net-next v6 11/17] dt-bindings: net: pse-pd: Add another
way of describing several PSE PIs
On Tue, Apr 02, 2024 at 08:26:37AM -0500, Rob Herring wrote:
> > + pairsets:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description:
> > + List of phandles, each pointing to the power supply for the
> > + corresponding pairset named in 'pairset-names'. This property
> > + aligns with IEEE 802.3-2022, Section 33.2.3 and 145.2.4.
> > + PSE Pinout Alternatives (as per IEEE 802.3-2022 Table 145\u20133)
> > + |-----------|---------------|---------------|---------------|---------------|
> > + | Conductor | Alternative A | Alternative A | Alternative B | Alternative B |
> > + | | (MDI-X) | (MDI) | (X) | (S) |
> > + |-----------|---------------|---------------|---------------|---------------|
> > + | 1 | Negative VPSE | Positive VPSE | \u2014 | \u2014 |
> > + | 2 | Negative VPSE | Positive VPSE | \u2014 | \u2014 |
> > + | 3 | Positive VPSE | Negative VPSE | \u2014 | \u2014 |
> > + | 4 | \u2014 | \u2014 | Negative VPSE | Positive VPSE |
> > + | 5 | \u2014 | \u2014 | Negative VPSE | Positive VPSE |
> > + | 6 | Positive VPSE | Negative VPSE | \u2014 | \u2014 |
> > + | 7 | \u2014 | \u2014 | Positive VPSE | Negative VPSE |
> > + | 8 | \u2014 | \u2014 | Positive VPSE | Negative VPSE |
> > + minItems: 1
> > + maxItems: 2
>
> "pairsets" does not follow the normal design pattern of foos, foo-names,
> and #foo-cells. You could add #foo-cells I suppose, but what would cells
> convey? I don't think it's a good fit for what you need.
>
> The other oddity is the number of entries and the names are fixed. That
> is usually defined per consumer.
>
> As each entry is just a power rail, why can't the regulator binding be
> used here?
I'm not against describing it consequent with regulator till the wire
end, but right now I have no idea how it should be described by using
regulator bindings. There are maximum 2 rails going in to PSE PI on one
side and 4 rails with at least 5 combinations supported by standard on
other side. Instead of inventing anything new, I suggested to describe
supported output combinations by using IEEE 802.3 standard.
Regards,
Oleksij
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