| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 2 Apr 2024 20:15:55 +0100 From: Jon Hunter <jonathanh@...dia.com> To: Sumit Gupta <sumitg@...dia.com>, krzysztof.kozlowski@...aro.org, robh@...nel.org, conor+dt@...nel.org, maz@...nel.org, mark.rutland@....com, treding@...dia.com Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org, amhetre@...dia.com, bbasu@...dia.com Subject: Re: [Patch v2 1/2] dt-bindings: make sid and broadcast reg optional On 02/04/2024 14:26, Sumit Gupta wrote: > MC SID and Broadbast channel register access is restricted for Guest VM. > Make both the regions as optional for SoC's from Tegra186 onwards. > Tegra MC driver will skip access to the restricted registers from Guest > if the respective regions are not present in the memory-controller node > of Guest DT. > > Signed-off-by: Sumit Gupta <sumitg@...dia.com> > --- > .../memory-controllers/nvidia,tegra186-mc.yaml | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > index 935d63d181d9..c52c259f7ec5 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml > @@ -146,17 +146,17 @@ allOf: > then: > properties: > reg: > - maxItems: 6 > + maxItems: 4 minItems? Jon -- nvpublic
Powered by blists - more mailing lists