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Message-ID: <ZgvkRFxkNzQ2Z8re@dragon>
Date: Tue, 2 Apr 2024 18:56:04 +0800
From: Shawn Guo <shawnguo2@...h.net>
To: Frank Li <Frank.Li@....com>
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Dong Aisheng <aisheng.dong@....com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
"open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <imx@...ts.linux.dev>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/1] arm64: dts: imx8-ss-conn: fix usdhc wrong lpcg clock
order
On Fri, Mar 22, 2024 at 12:47:05PM -0400, Frank Li wrote:
> The actual clock show wrong frequency:
>
> echo on >/sys/devices/platform/bus\@5b000000/5b010000.mmc/power/control
> cat /sys/kernel/debug/mmc0/ios
>
> clock: 200000000 Hz
> actual clock: 166000000 Hz
> ^^^^^^^^^
> .....
>
> According to
>
> sdhc0_lpcg: clock-controller@...00000 {
> compatible = "fsl,imx8qxp-lpcg";
> reg = <0x5b200000 0x10000>;
> #clock-cells = <1>;
> clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
> <&conn_ipg_clk>, <&conn_axi_clk>;
> clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
> <IMX_LPCG_CLK_5>;
> clock-output-names = "sdhc0_lpcg_per_clk",
> "sdhc0_lpcg_ipg_clk",
> "sdhc0_lpcg_ahb_clk";
> power-domains = <&pd IMX_SC_R_SDHC_0>;
> }
>
> "per_clk" should be IMX_LPCG_CLK_0 instead of IMX_LPCG_CLK_5.
>
> After correct clocks order:
>
> echo on >/sys/devices/platform/bus\@5b000000/5b010000.mmc/power/control
> cat /sys/kernel/debug/mmc0/ios
>
> clock: 200000000 Hz
> actual clock: 198000000 Hz
> ^^^^^^^^
> ...
>
> Fixes: 16c4ea7501b1 ("arm64: dts: imx8: switch to new lpcg clock binding")
> Signed-off-by: Frank Li <Frank.Li@....com>
Applied, thanks!
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