linux-kernel - Re: [PATCH v4 0/4] perf/x86/amd: add LBR capture support outside of hardware events

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Date: Wed, 3 Apr 2024 09:08:05 -0700
From: Andrii Nakryiko <andrii.nakryiko@...il.com>
To: Ingo Molnar <mingo@...nel.org>
Cc: Andrii Nakryiko <andrii@...nel.org>, x86@...nel.org, peterz@...radead.org, 
	mingo@...hat.com, tglx@...utronix.de, bpf@...r.kernel.org, 
	linux-kernel@...r.kernel.org, jolsa@...nel.org, song@...nel.org, 
	kernel-team@...a.com
Subject: Re: [PATCH v4 0/4] perf/x86/amd: add LBR capture support outside of
 hardware events

On Wed, Apr 3, 2024 at 1:06 AM Ingo Molnar <mingo@...nel.org> wrote:
>
>
> * Andrii Nakryiko <andrii.nakryiko@...il.com> wrote:
>
> > On Mon, Apr 1, 2024 at 2:30 AM Ingo Molnar <mingo@...nel.org> wrote:
> > >
> > >
> > > * Andrii Nakryiko <andrii@...nel.org> wrote:
> > >
> > > > Add AMD-specific implementation of perf_snapshot_branch_stack static call that
> > > > allows LBR capture from arbitrary points in the kernel. This is utilized by
> > > > BPF programs. See patch #3 for all the details.
> > > >
> > > > Patches #1 and #2 are preparatory steps to ensure LBR freezing is completely
> > > > inlined and have no branches, to minimize LBR snapshot contamination.
> > > >
> > > > Patch #4 removes an artificial restriction on perf events with LBR enabled.
> > > >
> > > > Andrii Nakryiko (4):
> > > >   perf/x86/amd: ensure amd_pmu_core_disable_all() is always inlined
> > > >   perf/x86/amd: avoid taking branches before disabling LBR
> > > >   perf/x86/amd: support capturing LBR from software events
> > > >   perf/x86/amd: don't reject non-sampling events with configured LBR
> > > >
> > > >  arch/x86/events/amd/core.c   | 37 +++++++++++++++++++++++++++++++++++-
> > > >  arch/x86/events/amd/lbr.c    | 11 +----------
> > > >  arch/x86/events/perf_event.h | 11 +++++++++++
> > > >  3 files changed, 48 insertions(+), 11 deletions(-)
> > >
> > > So there's a new conflict with patch #2, probably due to interaction
> > > with this recent fix that is now upstream:
> > >
> > >    598c2fafc06f ("perf/x86/amd/lbr: Use freeze based on availability")
> > >
> > > I don't think it should change the logic of the snapshot feature
> > > materially, X86_FEATURE_AMD_LBR_PMC_FREEZE should be orthogonal to it,
> > > as the LBR snapshot isn't taken from a PMI.
> > >
> >
> > Yep, seems like there was a parallel change to related code in
> > perf/urgent branch. And yes, you are right that it's orthogonal and
> > doesn't regress anything as far as branching and whatnot (just
> > retested everything on real hardware). So I've rebased my patches on
> > top of perf/urgent, will send v5 momentarily.
>
> Thank you - it's now all in tip:perf/core and lined up for v6.10.

Great, thank you!

>
> > Sorry for an extra round on this.
>
> Not your doing really - just crossing patches.
>
> Thanks,
>
>         Ingo