[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <f0dcfd6a-55cf-84d8-6599-319a700e1960@quicinc.com>
Date: Wed, 3 Apr 2024 10:23:59 -0700
From: Kuogee Hsieh <quic_khsieh@...cinc.com>
To: <dri-devel@...ts.freedesktop.org>, <robdclark@...il.com>,
<sean@...rly.run>, <swboyd@...omium.org>, <dianders@...omium.org>,
<vkoul@...nel.org>, <daniel@...ll.ch>, <airlied@...il.com>,
<agross@...nel.org>, <dmitry.baryshkov@...aro.org>,
<abel.vesa@...aro.org>, <andersson@...nel.org>
CC: <quic_abhinavk@...cinc.com>, <quic_jesszhan@...cinc.com>,
<quic_sbillaka@...cinc.com>, <marijn.suijten@...ainline.org>,
<freedreno@...ts.freedesktop.org>, <linux-arm-msm@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3] drm/msm/dp: assign correct DP controller ID to
x1e80100 interface table
Dmitry,
any more comments?
On 3/29/2024 12:46 PM, Kuogee Hsieh wrote:
> At current x1e80100 interface table, interface #3 is wrongly
> connected to DP controller #0 and interface #4 wrongly connected
> to DP controller #2. Fix this problem by connect Interface #3 to
> DP controller #0 and interface #4 connect to DP controller #1.
> Also add interface #6, #7 and #8 connections to DP controller to
> complete x1e80100 interface table.
>
> Changs in V3:
> -- add v2 changes log
>
> Changs in V2:
> -- add x1e80100 to subject
> -- add Fixes
>
> Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support")
> Signed-off-by: Kuogee Hsieh <quic_khsieh@...cinc.com>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
> Reviewed-by: Abel Vesa <abel.vesa@...aro.org>
> ---
> .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 34 ++++++++++++++++++++--
> 1 file changed, 31 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 9a9f709..a3e60ac 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -324,6 +324,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = {
> },
> };
>
> +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
> static const struct dpu_intf_cfg x1e80100_intf[] = {
> {
> .name = "intf_0", .id = INTF_0,
> @@ -358,8 +359,8 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> .name = "intf_3", .id = INTF_3,
> .base = 0x37000, .len = 0x280,
> .features = INTF_SC7280_MASK,
> - .type = INTF_DP,
> - .controller_id = MSM_DP_CONTROLLER_1,
> + .type = INTF_NONE,
> + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
> .prog_fetch_lines_worst_case = 24,
> .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
> .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
> @@ -368,7 +369,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> .base = 0x38000, .len = 0x280,
> .features = INTF_SC7280_MASK,
> .type = INTF_DP,
> - .controller_id = MSM_DP_CONTROLLER_2,
> + .controller_id = MSM_DP_CONTROLLER_1,
> .prog_fetch_lines_worst_case = 24,
> .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
> .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
> @@ -381,6 +382,33 @@ static const struct dpu_intf_cfg x1e80100_intf[] = {
> .prog_fetch_lines_worst_case = 24,
> .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
> .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
> + }, {
> + .name = "intf_6", .id = INTF_6,
> + .base = 0x3A000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_DP,
> + .controller_id = MSM_DP_CONTROLLER_2,
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
> + }, {
> + .name = "intf_7", .id = INTF_7,
> + .base = 0x3b000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_NONE,
> + .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
> + }, {
> + .name = "intf_8", .id = INTF_8,
> + .base = 0x3c000, .len = 0x280,
> + .features = INTF_SC7280_MASK,
> + .type = INTF_NONE,
> + .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */
> + .prog_fetch_lines_worst_case = 24,
> + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
> + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
> },
> };
>
Powered by blists - more mailing lists