lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20240403080452.1007601-11-atishp@rivosinc.com>
Date: Wed,  3 Apr 2024 01:04:39 -0700
From: Atish Patra <atishp@...osinc.com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atishp@...osinc.com>,
	Anup Patel <anup@...infault.org>,
	Andrew Jones <ajones@...tanamicro.com>,
	Ajay Kaher <akaher@...are.com>,
	Alexandre Ghiti <alexghiti@...osinc.com>,
	Alexey Makhalov <amakhalov@...are.com>,
	Conor Dooley <conor.dooley@...rochip.com>,
	Juergen Gross <jgross@...e.com>,
	kvm-riscv@...ts.infradead.org,
	kvm@...r.kernel.org,
	linux-kselftest@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	Mark Rutland <mark.rutland@....com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Paolo Bonzini <pbonzini@...hat.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Shuah Khan <shuah@...nel.org>,
	virtualization@...ts.linux.dev,
	VMware PV-Drivers Reviewers <pv-drivers@...are.com>,
	Will Deacon <will@...nel.org>,
	x86@...nel.org
Subject: [PATCH v5 10/22] RISC-V: KVM: No need to update the counter value during reset

The virtual counter value is updated during pmu_ctr_read. There is no need
to update it in reset case. Otherwise, it will be counted twice which is
incorrect.

Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling")
Reviewed-by: Anup Patel <anup@...infault.org>
Reviewed-by: Andrew Jones <ajones@...tanamicro.com>
Signed-off-by: Atish Patra <atishp@...osinc.com>
---
 arch/riscv/kvm/vcpu_pmu.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
index cee1b9ca4ec4..b5159ce4592d 100644
--- a/arch/riscv/kvm/vcpu_pmu.c
+++ b/arch/riscv/kvm/vcpu_pmu.c
@@ -397,7 +397,6 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
 {
 	struct kvm_pmu *kvpmu = vcpu_to_pmu(vcpu);
 	int i, pmc_index, sbiret = 0;
-	u64 enabled, running;
 	struct kvm_pmc *pmc;
 	int fevent_code;
 
@@ -432,12 +431,9 @@ int kvm_riscv_vcpu_pmu_ctr_stop(struct kvm_vcpu *vcpu, unsigned long ctr_base,
 				sbiret = SBI_ERR_ALREADY_STOPPED;
 			}
 
-			if (flags & SBI_PMU_STOP_FLAG_RESET) {
-				/* Relase the counter if this is a reset request */
-				pmc->counter_val += perf_event_read_value(pmc->perf_event,
-									  &enabled, &running);
+			if (flags & SBI_PMU_STOP_FLAG_RESET)
+				/* Release the counter if this is a reset request */
 				kvm_pmu_release_perf_event(pmc);
-			}
 		} else {
 			sbiret = SBI_ERR_INVALID_PARAM;
 		}
-- 
2.34.1


Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ