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Message-ID: <16d21771-dded-4c1d-90b0-f3ac03be0726@kernel.org>
Date: Fri, 5 Apr 2024 09:59:34 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Peter Griffin <peter.griffin@...aro.org>, mturquette@...libre.com,
 sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
 vkoul@...nel.org, kishon@...nel.org, alim.akhtar@...sung.com,
 avri.altman@....com, bvanassche@....org, s.nawrocki@...sung.com,
 cw00.choi@...sung.com, jejb@...ux.ibm.com, martin.petersen@...cle.com,
 chanho61.park@...sung.com, ebiggers@...nel.org
Cc: linux-scsi@...r.kernel.org, linux-phy@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, tudor.ambarus@...aro.org,
 andre.draszik@...aro.org, saravanak@...gle.com, willmcvicker@...gle.com
Subject: Re: [PATCH 16/17] scsi: ufs: host: ufs-exynos: Add support for Tensor
 gs101 SoC

On 04/04/2024 14:25, Peter Griffin wrote:
> Add a dedicated compatible and drv_data with associated
> hooks for gs101 SoC found on Pixel 6.
> 
> Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
> option, to skip initialisation of UFSPR registers as these are only
> accessible via SMC call.
> 
> EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
> source. This has been done so as not to effect any existing platforms.
> 
> DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs
> so these register offsets now come from uic_attr struct.
> 
> Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
> ---


Acked-by: Krzysztof Kozlowski <krzk@...nel.org>

Best regards,
Krzysztof


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