linux-kernel - Re: [PATCH v2 3/5] media: chips-media: wave5: separate irq setup routine

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20240405092950.wt5cvhvhiujicc5h@basti-XPS-13-9310>
Date: Fri, 5 Apr 2024 11:29:50 +0200
From: Sebastian Fricke <sebastian.fricke@...labora.com>
To: Ivan Bornyakov <brnkv.i1@...il.com>
Cc: Nas Chung <nas.chung@...psnmedia.com>,
	Jackson Lee <jackson.lee@...psnmedia.com>,
	Mauro Carvalho Chehab <mchehab@...nel.org>,
	Philipp Zabel <p.zabel@...gutronix.de>, linux-media@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/5] media: chips-media: wave5: separate irq setup
 routine

Hey Ivan,

On 25.03.2024 09:40, Ivan Bornyakov wrote:
>Separate interrupts setup routine to reduce code duplication. Also

s/Separate interrupts setup routine/Implement a separate setup routine for interrupts/

>enable interrupts based on vpu_attr->support_encoders and
>vpu_attr->support_decoders fields to facilitate other Wave5xx IPs
>support, because not all of them are both encoders and decoders.

s/other Wave5xx IPs support/support for other Wave5xx IPs/

The rest looks good to me.

Greetings,
Sebastian

>
>Signed-off-by: Ivan Bornyakov <brnkv.i1@...il.com>
>---
> .../platform/chips-media/wave5/wave5-hw.c     | 53 +++++++++----------
> 1 file changed, 24 insertions(+), 29 deletions(-)
>
>diff --git a/drivers/media/platform/chips-media/wave5/wave5-hw.c b/drivers/media/platform/chips-media/wave5/wave5-hw.c
>index 2d82791f575e..cdd0a0948a94 100644
>--- a/drivers/media/platform/chips-media/wave5/wave5-hw.c
>+++ b/drivers/media/platform/chips-media/wave5/wave5-hw.c
>@@ -299,6 +299,27 @@ static int wave5_send_query(struct vpu_device *vpu_dev, struct vpu_instance *ins
> 	return wave5_vpu_firmware_command_queue_error_check(vpu_dev, NULL);
> }
>
>+static void setup_wave5_interrupts(struct vpu_device *vpu_dev)
>+{
>+	u32 reg_val = 0;
>+
>+	if (vpu_dev->attr.support_encoders) {
>+		/* Encoder interrupt */
>+		reg_val |= BIT(INT_WAVE5_ENC_SET_PARAM);
>+		reg_val |= BIT(INT_WAVE5_ENC_PIC);
>+		reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
>+	}
>+
>+	if (vpu_dev->attr.support_decoders) {
>+		/* Decoder interrupt */
>+		reg_val |= BIT(INT_WAVE5_INIT_SEQ);
>+		reg_val |= BIT(INT_WAVE5_DEC_PIC);
>+		reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
>+	}
>+
>+	return vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
>+}
>+
> static int setup_wave5_properties(struct device *dev)
> {
> 	struct vpu_device *vpu_dev = dev_get_drvdata(dev);
>@@ -340,6 +361,8 @@ static int setup_wave5_properties(struct device *dev)
> 	p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0);
> 	p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0);
>
>+	setup_wave5_interrupts(vpu_dev);
>+
> 	return 0;
> }
>
>@@ -417,16 +440,6 @@ int wave5_vpu_init(struct device *dev, u8 *fw, size_t size)
> 	wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
> 	vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
>
>-	/* Encoder interrupt */
>-	reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
>-	reg_val |= BIT(INT_WAVE5_ENC_PIC);
>-	reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
>-	/* Decoder interrupt */
>-	reg_val |= BIT(INT_WAVE5_INIT_SEQ);
>-	reg_val |= BIT(INT_WAVE5_DEC_PIC);
>-	reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
>-	vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
>-
> 	reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
> 	if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
> 		reg_val = ((WAVE5_PROC_AXI_ID << 28) |
>@@ -1034,16 +1047,6 @@ int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size)
> 		wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
> 		vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
>
>-		/* Encoder interrupt */
>-		reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
>-		reg_val |= BIT(INT_WAVE5_ENC_PIC);
>-		reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
>-		/* Decoder interrupt */
>-		reg_val |= BIT(INT_WAVE5_INIT_SEQ);
>-		reg_val |= BIT(INT_WAVE5_DEC_PIC);
>-		reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
>-		vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
>-
> 		reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
> 		if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
> 			reg_val = ((WAVE5_PROC_AXI_ID << 28) |
>@@ -1134,15 +1137,7 @@ static int wave5_vpu_sleep_wake(struct device *dev, bool i_sleep_wake, const uin
> 		wave5_fio_writel(vpu_dev, W5_BACKBONE_AXI_PARAM, 0);
> 		vpu_write_reg(vpu_dev, W5_SEC_AXI_PARAM, 0);
>
>-		/* Encoder interrupt */
>-		reg_val = BIT(INT_WAVE5_ENC_SET_PARAM);
>-		reg_val |= BIT(INT_WAVE5_ENC_PIC);
>-		reg_val |= BIT(INT_WAVE5_BSBUF_FULL);
>-		/* Decoder interrupt */
>-		reg_val |= BIT(INT_WAVE5_INIT_SEQ);
>-		reg_val |= BIT(INT_WAVE5_DEC_PIC);
>-		reg_val |= BIT(INT_WAVE5_BSBUF_EMPTY);
>-		vpu_write_reg(vpu_dev, W5_VPU_VINT_ENABLE, reg_val);
>+		setup_wave5_interrupts(vpu_dev);
>
> 		reg_val = vpu_read_reg(vpu_dev, W5_VPU_RET_VPU_CONFIG0);
> 		if (FIELD_GET(FEATURE_BACKBONE, reg_val)) {
>-- 
>2.44.0
>
>