linux-kernel - Re: [PATCH] arm64: Fix double TCR_T0SZ

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Message-ID: <94af4af9-8cef-4673-bce5-16bd5edb28dd@arm.com>
Date: Fri, 5 Apr 2024 15:10:41 +0100
From: Robin Murphy <robin.murphy@....com>
To: Seongsu Park <sgsu.park@...sung.com>, catalin.marinas@....com,
 will@...nel.org, ardb@...nel.org, mark.rutland@....com
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 Leem ChaeHoon <infinite.run@...il.com>,
 Gyeonggeon Choi <gychoi@...dent.42seoul.kr>, Soomin Cho
 <to.soomin@...il.com>, DaeRo Lee <skseofh@...il.com>,
 kmasta <kmasta.study@...il.com>
Subject: Re: [PATCH] arm64: Fix double TCR_T0SZ_OFFSET shift

On 2024-04-02 11:47 am, Seongsu Park wrote:
> We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET.
> So, the TCR_T0SZ_OFFSET shift here should be removed.

If the shift for assigning the t0sz value to the TCR field is wrong, 
then the other shift for comparing the same t0sz value to the existing 
TCR field must also be wrong. Really, this many people involved in 
writing a patch and still nobody spotted the obvious?

Thanks,
Robin.

> Co-developed-by: Leem ChaeHoon <infinite.run@...il.com>
> Signed-off-by: Leem ChaeHoon <infinite.run@...il.com>
> Co-developed-by: Gyeonggeon Choi <gychoi@...dent.42seoul.kr>
> Signed-off-by: Gyeonggeon Choi <gychoi@...dent.42seoul.kr>
> Co-developed-by: Soomin Cho <to.soomin@...il.com>
> Signed-off-by: Soomin Cho <to.soomin@...il.com>
> Co-developed-by: DaeRo Lee <skseofh@...il.com>
> Signed-off-by: DaeRo Lee <skseofh@...il.com>
> Co-developed-by: kmasta <kmasta.study@...il.com>
> Signed-off-by: kmasta <kmasta.study@...il.com>
> Signed-off-by: Seongsu Park <sgsu.park@...sung.com>
> ---
>   arch/arm64/include/asm/mmu_context.h | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
> index c768d16b81a4..58de99836d2e 100644
> --- a/arch/arm64/include/asm/mmu_context.h
> +++ b/arch/arm64/include/asm/mmu_context.h
> @@ -76,7 +76,7 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
>   		return;
>   
>   	tcr &= ~TCR_T0SZ_MASK;
> -	tcr |= t0sz << TCR_T0SZ_OFFSET;
> +	tcr |= t0sz;
>   	write_sysreg(tcr, tcr_el1);
>   	isb();
>   }