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Message-ID: <20240407-opp_support-v9-3-496184dc45d7@quicinc.com>
Date: Sun, 7 Apr 2024 10:07:36 +0530
From: Krishna chaitanya chundru <quic_krichai@...cinc.com>
To: Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio
<konrad.dybcio@...aro.org>,
Rob Herring <robh@...nel.org>,
"Krzysztof
Kozlowski" <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley
<conor+dt@...nel.org>,
Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org>,
Lorenzo Pieralisi
<lpieralisi@...nel.org>,
Krzysztof WilczyĆski
<kw@...ux.com>,
Bjorn Helgaas <bhelgaas@...gle.com>, <johan+linaro@...nel.org>,
<bmasney@...hat.com>, <djakov@...nel.org>
CC: <linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>,
<vireshk@...nel.org>, <quic_vbadigan@...cinc.com>,
<quic_skananth@...cinc.com>, <quic_nitegupt@...cinc.com>,
<quic_parass@...cinc.com>, <quic_krichai@...cinc.com>,
<krzysztof.kozlowski@...aro.org>
Subject: [PATCH v9 3/6] dt-bindings: pci: qcom: Add opp table
PCIe needs to choose the appropriate performance state of RPMH power
domain based upon the PCIe gen speed.
Adding the Operating Performance Points table allows to adjust power
domain performance state and icc peak bw, depending on the PCIe gen
speed and width.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@...cinc.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
index 1496d6993ab4..d8c0afaa4b19 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
@@ -69,6 +69,10 @@ properties:
- const: msi6
- const: msi7
+ operating-points-v2: true
+ opp-table:
+ type: object
+
resets:
maxItems: 1
--
2.42.0
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