lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20240408093930.45422bc1@jacob-builder>
Date: Mon, 8 Apr 2024 09:39:30 -0700
From: Jacob Pan <jacob.jun.pan@...ux.intel.com>
To: "Tian, Kevin" <kevin.tian@...el.com>
Cc: Baolu Lu <baolu.lu@...ux.intel.com>, Dimitri Sivanich
 <sivanich@....com>, Thomas Gleixner <tglx@...utronix.de>, Joerg Roedel
 <joro@...tes.org>, Suravee Suthikulpanit <suravee.suthikulpanit@....com>,
 Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, David
 Woodhouse <dwmw2@...radead.org>, Mark Rutland <mark.rutland@....com>, Peter
 Zijlstra <peterz@...radead.org>, Arnd Bergmann <arnd@...db.de>, YueHaibing
 <yuehaibing@...wei.com>, "iommu@...ts.linux.dev" <iommu@...ts.linux.dev>,
 "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Steve Wahl
 <steve.wahl@....com>, "Anderson, Russ" <russ.anderson@....com>,
 jacob.jun.pan@...ux.intel.com
Subject: Re: [PATCH v2] iommu/vt-d: Allocate DMAR fault interrupts locally

Hi Kevin,

On Mon, 8 Apr 2024 09:00:05 +0000, "Tian, Kevin" <kevin.tian@...el.com>
wrote:

> > From: Baolu Lu <baolu.lu@...ux.intel.com>
> > Sent: Monday, April 8, 2024 3:22 PM
> > 
> > On 2024/4/8 14:54, Tian, Kevin wrote:  
> > >> From: Dimitri Sivanich <sivanich@....com>
> > >> Sent: Friday, March 22, 2024 4:51 AM
> > >>
> > >> The Intel IOMMU code currently tries to allocate all DMAR fault
> > >> interrupt vectors on the boot cpu.  On large systems with high DMAR
> > >> counts this results in vector exhaustion, and most of the vectors
> > >> are not initially allocated socket local.
> > >>
> > >> Instead, have a cpu on each node do the vector allocation for the
> > >> DMARs  
> > on  
> > >> that node.  The boot cpu still does the allocation for its node
> > >> during its boot sequence.
> > >>
> > >> Signed-off-by: Dimitri Sivanich <sivanich@....com>  
> > >
> > > Reviewed-by: Kevin Tian <kevin.tian@...el.com>
> > >  
> > 
> > Kevin,
> > 
> > Jacob has another proposal which shares the irq among all IOMMUs.
> > 
> > https://lore.kernel.org/linux-iommu/20240403234548.989061-1-
> > jacob.jun.pan@...ux.intel.com/
> > 
> > How do you like this?
> >   
> 
> I'm a bit concerning about the need of looping all IOMMU's in DMAR
> irqchip mask/unmask handlers. this one sounds simpler to me.
The difference is that with this patch, we still burn a few vectors on BSP
and the leading CPU of each socket.

e.g. on sapphire rapids, we lose 8 vectors to DMAR fault IRQ on BSP.

Thanks,

Jacob

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ