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Message-ID: <20240409-underrate-armless-697047fd61cc@spud>
Date: Tue, 9 Apr 2024 16:03:34 +0100
From: Conor Dooley <conor@...nel.org>
To: Samuel Holland <samuel.holland@...ive.com>
Cc: Will Deacon <will@...nel.org>, Mark Rutland <mark.rutland@....com>,
Eric Lin <eric.lin@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv@...ts.infradead.org, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v1 1/6] dt-bindings: cache: Document the
sifive,perfmon-counters property
On Thu, Feb 15, 2024 at 04:08:13PM -0800, Samuel Holland wrote:
> The SiFive Composable Cache controller contains an optional PMU with a
> configurable number of event counters. Document a property which
> describes the number of available counters.
>
> Signed-off-by: Samuel Holland <samuel.holland@...ive.com>
> ---
>
> Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> index 7e8cebe21584..100eda4345de 100644
> --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
> @@ -81,6 +81,11 @@ properties:
> The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
> The reserved memory node should be defined as per the bindings in reserved-memory.txt.
>
> + sifive,perfmon-counters:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> + description: Number of PMU counter registers
I think this should be restricted to devices that actually have it,
given we've already gone pretty hard in this binding with specific
requirements.
> +
> allOf:
> - $ref: /schemas/cache-controller.yaml#
>
> --
> 2.43.0
>
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