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Message-ID: <d228494c-5ac6-455b-95c7-3c53c589dd6a@intel.com>
Date: Thu, 11 Apr 2024 07:29:06 -0700
From: Dave Hansen <dave.hansen@...el.com>
To: Mathieu Desnoyers <mathieu.desnoyers@...icios.com>,
Ingo Molnar <mingo@...hat.com>, Peter Zijlstra <peterz@...radead.org>,
Thomas Gleixner <tglx@...utronix.de>, Borislav Petkov <bp@...en8.de>,
Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org,
"H . Peter Anvin" <hpa@...or.com>
Cc: linux-kernel@...r.kernel.org, "levi . yun" <yeoreum.yun@....com>,
stable@...r.kernel.org, Steven Rostedt <rostedt@...dmis.org>,
Vincent Guittot <vincent.guittot@...aro.org>,
Juri Lelli <juri.lelli@...hat.com>,
Dietmar Eggemann <dietmar.eggemann@....com>, Ben Segall
<bsegall@...gle.com>, Mel Gorman <mgorman@...e.de>,
Daniel Bristot de Oliveira <bristot@...hat.com>,
Valentin Schneider <vschneid@...hat.com>,
Catalin Marinas <catalin.marinas@....com>,
Mark Rutland <mark.rutland@....com>, Will Deacon <will@...nel.org>,
Aaron Lu <aaron.lu@...el.com>
Subject: Re: [PATCH] sched: Add missing memory barrier in switch_mm_cid
On 4/10/24 10:18, Mathieu Desnoyers wrote:
> --- a/arch/x86/include/asm/barrier.h
> +++ b/arch/x86/include/asm/barrier.h
> @@ -79,6 +79,9 @@ do { \
> #define __smp_mb__before_atomic() do { } while (0)
> #define __smp_mb__after_atomic() do { } while (0)
> +/* Writing to CR3 provides a full memory barrier in switch_mm(). */
> +#define smp_mb__after_switch_mm() do { } while (0)
I haven't gone through this in detail, but the CR3 certainly is a full
barrier and the x86 code _looks_ correct, so:
Acked-by: Dave Hansen <dave.hansen@...ux.intel.com> # for x86
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