linux-kernel - Re: [RFC PATCH 00/41] KVM: x86/pmu: Introduce passthrough vPM

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Message-ID: <Zhhxg7VvBD38nymZ@google.com>
Date: Thu, 11 Apr 2024 16:25:55 -0700
From: Sean Christopherson <seanjc@...gle.com>
To: Xiong Zhang <xiong.y.zhang@...ux.intel.com>
Cc: pbonzini@...hat.com, peterz@...radead.org, mizhang@...gle.com, 
	kan.liang@...el.com, zhenyuw@...ux.intel.com, dapeng1.mi@...ux.intel.com, 
	jmattson@...gle.com, kvm@...r.kernel.org, linux-perf-users@...r.kernel.org, 
	linux-kernel@...r.kernel.org, zhiyuan.lv@...el.com, eranian@...gle.com, 
	irogers@...gle.com, samantha.alt@...el.com, like.xu.linux@...il.com, 
	chao.gao@...el.com
Subject: Re: [RFC PATCH 00/41] KVM: x86/pmu: Introduce passthrough vPM

On Fri, Jan 26, 2024, Xiong Zhang wrote:
> Dapeng Mi (4):
>   x86: Introduce MSR_CORE_PERF_GLOBAL_STATUS_SET for passthrough PMU
>   KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU
>   KVM: x86/pmu: Introduce macro PMU_CAP_PERF_METRICS
>   KVM: x86/pmu: Clear PERF_METRICS MSR for guest
> 
> Kan Liang (2):
>   perf: x86/intel: Support PERF_PMU_CAP_VPMU_PASSTHROUGH
>   perf: Support guest enter/exit interfaces
> 
> Mingwei Zhang (22):
>   perf: core/x86: Forbid PMI handler when guest own PMU
>   perf: core/x86: Plumb passthrough PMU capability from x86_pmu to
>     x86_pmu_cap
>   KVM: x86/pmu: Introduce enable_passthrough_pmu module parameter and
>     propage to KVM instance
>   KVM: x86/pmu: Plumb through passthrough PMU to vcpu for Intel CPUs
>   KVM: x86/pmu: Add a helper to check if passthrough PMU is enabled
>   KVM: x86/pmu: Allow RDPMC pass through
>   KVM: x86/pmu: Create a function prototype to disable MSR interception
>   KVM: x86/pmu: Implement pmu function for Intel CPU to disable MSR
>     interception
>   KVM: x86/pmu: Intercept full-width GP counter MSRs by checking with
>     perf capabilities
>   KVM: x86/pmu: Whitelist PMU MSRs for passthrough PMU
>   KVM: x86/pmu: Introduce PMU operation prototypes for save/restore PMU
>     context
>   KVM: x86/pmu: Introduce function prototype for Intel CPU to
>     save/restore PMU context
>   KVM: x86/pmu: Zero out unexposed Counters/Selectors to avoid
>     information leakage
>   KVM: x86/pmu: Add host_perf_cap field in kvm_caps to record host PMU
>     capability
>   KVM: x86/pmu: Exclude existing vLBR logic from the passthrough PMU
>   KVM: x86/pmu: Make check_pmu_event_filter() an exported function
>   KVM: x86/pmu: Allow writing to event selector for GP counters if event
>     is allowed
>   KVM: x86/pmu: Allow writing to fixed counter selector if counter is
>     exposed
>   KVM: x86/pmu: Introduce PMU helper to increment counter
>   KVM: x86/pmu: Implement emulated counter increment for passthrough PMU
>   KVM: x86/pmu: Separate passthrough PMU logic in set/get_msr() from
>     non-passthrough vPMU
>   KVM: nVMX: Add nested virtualization support for passthrough PMU
> 
> Xiong Zhang (13):
>   perf: Set exclude_guest onto nmi_watchdog
>   perf: core/x86: Add support to register a new vector for PMI handling
>   KVM: x86/pmu: Register PMI handler for passthrough PMU
>   perf: x86: Add function to switch PMI handler
>   perf/x86: Add interface to reflect virtual LVTPC_MASK bit onto HW
>   KVM: x86/pmu: Add get virtual LVTPC_MASK bit function
>   KVM: x86/pmu: Manage MSR interception for IA32_PERF_GLOBAL_CTRL
>   KVM: x86/pmu: Switch IA32_PERF_GLOBAL_CTRL at VM boundary
>   KVM: x86/pmu: Switch PMI handler at KVM context switch boundary
>   KVM: x86/pmu: Call perf_guest_enter() at PMU context switch
>   KVM: x86/pmu: Add support for PMU context switch at VM-exit/enter
>   KVM: x86/pmu: Intercept EVENT_SELECT MSR
>   KVM: x86/pmu: Intercept FIXED_CTR_CTRL MSR

All done with this pass.  Looks quite good, nothing on the KVM side scares me.  Nice!

I haven't spent much time thinking about whether or not the overall implementation
correct/optimal, i.e. I mostly just reviewed the mechanics.  I'll make sure to
spend a bit more time on that for the next RFC.

Please be sure to rebase to kvm-x86/next for the next RFC, there are a few patches
that will change quite a bit.