| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20240411070503.38093-7-mmyangfl@gmail.com>
Date: Thu, 11 Apr 2024 15:04:50 +0800
From: David Yang <mmyangfl@...il.com>
To: linux-clk@...r.kernel.org
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
linux-kernel@...r.kernel.org,
David Yang <mmyangfl@...il.com>
Subject: [PATCH v8 05/13] clk: hisilicon: hi3519: Use helper functions
Use common helper functions and register clks with a single of_device_id
data.
Signed-off-by: David Yang <mmyangfl@...il.com>
---
drivers/clk/hisilicon/clk-hi3519.c | 127 ++++-------------------------
1 file changed, 15 insertions(+), 112 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c
index 141b727ff60d..cb541de752da 100644
--- a/drivers/clk/hisilicon/clk-hi3519.c
+++ b/drivers/clk/hisilicon/clk-hi3519.c
@@ -10,7 +10,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include "clk.h"
-#include "reset.h"
+#include "crg.h"
#define HI3519_INNER_CLK_OFFSET 64
#define HI3519_FIXED_24M 65
@@ -73,130 +73,33 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = {
CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
};
-static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)
-{
- struct hisi_clock_data *clk_data;
- int ret;
-
- clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS);
- if (!clk_data)
- return ERR_PTR(-ENOMEM);
-
- ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
- ARRAY_SIZE(hi3519_fixed_rate_clks),
- clk_data);
- if (ret)
- return ERR_PTR(ret);
-
- ret = hisi_clk_register_mux(hi3519_mux_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- clk_data);
- if (ret)
- goto unregister_fixed_rate;
-
- ret = hisi_clk_register_gate(hi3519_gate_clks,
- ARRAY_SIZE(hi3519_gate_clks),
- clk_data);
- if (ret)
- goto unregister_mux;
-
- ret = of_clk_add_provider(pdev->dev.of_node,
- of_clk_src_onecell_get, &clk_data->clk_data);
- if (ret)
- goto unregister_gate;
-
- return clk_data;
-
-unregister_fixed_rate:
- hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
- ARRAY_SIZE(hi3519_fixed_rate_clks),
- clk_data);
-
-unregister_mux:
- hisi_clk_unregister_mux(hi3519_mux_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- clk_data);
-unregister_gate:
- hisi_clk_unregister_gate(hi3519_gate_clks,
- ARRAY_SIZE(hi3519_gate_clks),
- clk_data);
- return ERR_PTR(ret);
-}
-
-static void hi3519_clk_unregister(struct platform_device *pdev)
-{
- struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
-
- of_clk_del_provider(pdev->dev.of_node);
-
- hisi_clk_unregister_gate(hi3519_gate_clks,
- ARRAY_SIZE(hi3519_gate_clks),
- crg->clk_data);
- hisi_clk_unregister_mux(hi3519_mux_clks,
- ARRAY_SIZE(hi3519_mux_clks),
- crg->clk_data);
- hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
- ARRAY_SIZE(hi3519_fixed_rate_clks),
- crg->clk_data);
-}
-
-static int hi3519_clk_probe(struct platform_device *pdev)
-{
- struct hi3519_crg_data *crg;
-
- crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
- if (!crg)
- return -ENOMEM;
-
- crg->rstc = hisi_reset_init(pdev);
- if (!crg->rstc)
- return -ENOMEM;
-
- crg->clk_data = hi3519_clk_register(pdev);
- if (IS_ERR(crg->clk_data)) {
- hisi_reset_exit(crg->rstc);
- return PTR_ERR(crg->clk_data);
- }
-
- platform_set_drvdata(pdev, crg);
- return 0;
-}
-
-static void hi3519_clk_remove(struct platform_device *pdev)
-{
- struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
-
- hisi_reset_exit(crg->rstc);
- hi3519_clk_unregister(pdev);
-}
-
+static const struct hisi_clocks hi3519_crg_clks = {
+ .nr = HI3519_NR_CLKS,
+ .fixed_rate_clks = hi3519_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3519_fixed_rate_clks),
+ .mux_clks = hi3519_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3519_mux_clks),
+ .gate_clks = hi3519_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3519_gate_clks),
+};
static const struct of_device_id hi3519_clk_match_table[] = {
- { .compatible = "hisilicon,hi3519-crg" },
+ { .compatible = "hisilicon,hi3519-crg",
+ .data = &hi3519_crg_clks },
{ }
};
MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
static struct platform_driver hi3519_clk_driver = {
- .probe = hi3519_clk_probe,
- .remove_new = hi3519_clk_remove,
+ .probe = hisi_crg_probe,
+ .remove_new = hisi_crg_remove,
.driver = {
.name = "hi3519-clk",
.of_match_table = hi3519_clk_match_table,
},
};
-static int __init hi3519_clk_init(void)
-{
- return platform_driver_register(&hi3519_clk_driver);
-}
-core_initcall(hi3519_clk_init);
-
-static void __exit hi3519_clk_exit(void)
-{
- platform_driver_unregister(&hi3519_clk_driver);
-}
-module_exit(hi3519_clk_exit);
+module_platform_driver(hi3519_clk_driver);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
--
2.43.0
Powered by blists - more mailing lists