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Message-ID: <20240411070503.38093-9-mmyangfl@gmail.com>
Date: Thu, 11 Apr 2024 15:04:52 +0800
From: David Yang <mmyangfl@...il.com>
To: linux-clk@...r.kernel.org
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
linux-kernel@...r.kernel.org,
David Yang <mmyangfl@...il.com>
Subject: [PATCH v8 07/13] clk: hisilicon: hi3660: Convert into module
Use common helper functions and register clks with a single of_device_id
data.
Signed-off-by: David Yang <mmyangfl@...il.com>
---
drivers/clk/hisilicon/clk-hi3660.c | 194 ++++++++---------------------
1 file changed, 54 insertions(+), 140 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
index 50f13dbb0e48..7fc5c16e5264 100644
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -5,9 +5,13 @@
*/
#include <dt-bindings/clock/hi3660-clock.h>
+
#include <linux/clk-provider.h>
-#include <linux/of.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
+
#include "clk.h"
static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
@@ -469,169 +473,79 @@ static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
CLK_SET_RATE_PARENT, 0x90, 0, 0, },
};
-static struct hisi_clock_data *clk_crgctrl_data;
-
-static void hi3660_clk_iomcu_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
- ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
- clk_data);
-}
-
-static void hi3660_clk_pmuctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
-
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
-
- hisi_clk_register_gate(hi3660_pmu_gate_clks,
- ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
-}
+static const struct hisi_clocks hi3660_clk_iomcu_clks = {
+ .gate_sep_clks = hi3660_iomcu_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
+};
-static void hi3660_clk_pctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
+static const struct hisi_clocks hi3660_clk_pmuctrl_clks = {
+ .gate_clks = hi3660_pmu_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_pmu_gate_clks),
+};
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
- hisi_clk_register_gate(hi3660_pctrl_gate_clks,
- ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
-}
+static const struct hisi_clocks hi3660_clk_pctrl_clks = {
+ .gate_clks = hi3660_pctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_pctrl_gate_clks),
+};
-static void hi3660_clk_sctrl_init(struct device_node *np)
-{
- struct hisi_clock_data *clk_data;
- int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
- ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
- ARRAY_SIZE(hi3660_sctrl_mux_clks) +
- ARRAY_SIZE(hi3660_sctrl_divider_clks);
+static const struct hisi_clocks hi3660_clk_sctrl_clks = {
+ .mux_clks = hi3660_sctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3660_sctrl_mux_clks),
+ .divider_clks = hi3660_sctrl_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3660_sctrl_divider_clks),
+ .gate_clks = hi3660_sctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_sctrl_gate_clks),
+ .gate_sep_clks = hi3660_sctrl_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
+};
- clk_data = hisi_clk_init(np, nr);
- if (!clk_data)
- return;
- hisi_clk_register_gate(hi3660_sctrl_gate_clks,
- ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
- hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
- ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
- clk_data);
- hisi_clk_register_mux(hi3660_sctrl_mux_clks,
- ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
- hisi_clk_register_divider(hi3660_sctrl_divider_clks,
- ARRAY_SIZE(hi3660_sctrl_divider_clks),
- clk_data);
-}
+static const struct hisi_clocks hi3660_clk_crgctrl_clks = {
+ .fixed_rate_clks = hi3660_fixed_rate_clks,
+ .fixed_rate_clks_num = ARRAY_SIZE(hi3660_fixed_rate_clks),
+ .fixed_factor_clks = hi3660_crg_fixed_factor_clks,
+ .fixed_factor_clks_num = ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
+ .mux_clks = hi3660_crgctrl_mux_clks,
+ .mux_clks_num = ARRAY_SIZE(hi3660_crgctrl_mux_clks),
+ .divider_clks = hi3660_crgctrl_divider_clks,
+ .divider_clks_num = ARRAY_SIZE(hi3660_crgctrl_divider_clks),
+ .gate_clks = hi3660_crgctrl_gate_clks,
+ .gate_clks_num = ARRAY_SIZE(hi3660_crgctrl_gate_clks),
+ .gate_sep_clks = hi3660_crgctrl_gate_sep_clks,
+ .gate_sep_clks_num = ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
+};
static void hi3660_clk_crgctrl_early_init(struct device_node *np)
{
- int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
- ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
- ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
- ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
- ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
- ARRAY_SIZE(hi3660_crgctrl_divider_clks);
- int i;
-
- clk_crgctrl_data = hisi_clk_init(np, nr);
- if (!clk_crgctrl_data)
- return;
-
- for (i = 0; i < nr; i++)
- clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER);
-
- hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
- ARRAY_SIZE(hi3660_fixed_rate_clks),
- clk_crgctrl_data);
+ hisi_clk_early_init(np, &hi3660_clk_crgctrl_clks);
}
CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl",
hi3660_clk_crgctrl_early_init);
-static void hi3660_clk_crgctrl_init(struct device_node *np)
-{
- struct clk **clks;
- int i;
-
- if (!clk_crgctrl_data)
- hi3660_clk_crgctrl_early_init(np);
-
- /* clk_crgctrl_data initialization failed */
- if (!clk_crgctrl_data)
- return;
-
- hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
- ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
- clk_crgctrl_data);
- hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
- ARRAY_SIZE(hi3660_crgctrl_gate_clks),
- clk_crgctrl_data);
- hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
- ARRAY_SIZE(hi3660_crgctrl_mux_clks),
- clk_crgctrl_data);
- hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
- ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
- clk_crgctrl_data);
- hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
- ARRAY_SIZE(hi3660_crgctrl_divider_clks),
- clk_crgctrl_data);
-
- clks = clk_crgctrl_data->clk_data.clks;
- for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) {
- if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER)
- pr_err("Failed to register crgctrl clock[%d] err=%ld\n",
- i, PTR_ERR(clks[i]));
- }
-}
-
static const struct of_device_id hi3660_clk_match_table[] = {
{ .compatible = "hisilicon,hi3660-crgctrl",
- .data = hi3660_clk_crgctrl_init },
+ .data = &hi3660_clk_crgctrl_clks },
{ .compatible = "hisilicon,hi3660-pctrl",
- .data = hi3660_clk_pctrl_init },
+ .data = &hi3660_clk_pctrl_clks },
{ .compatible = "hisilicon,hi3660-pmuctrl",
- .data = hi3660_clk_pmuctrl_init },
+ .data = &hi3660_clk_pmuctrl_clks },
{ .compatible = "hisilicon,hi3660-sctrl",
- .data = hi3660_clk_sctrl_init },
+ .data = &hi3660_clk_sctrl_clks },
{ .compatible = "hisilicon,hi3660-iomcu",
- .data = hi3660_clk_iomcu_init },
+ .data = &hi3660_clk_iomcu_clks },
{ }
};
-
-static int hi3660_clk_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
- void (*init_func)(struct device_node *np);
-
- init_func = of_device_get_match_data(dev);
- if (!init_func)
- return -ENODEV;
-
- init_func(np);
-
- return 0;
-}
+MODULE_DEVICE_TABLE(of, hi3660_clk_match_table);
static struct platform_driver hi3660_clk_driver = {
- .probe = hi3660_clk_probe,
+ .probe = hisi_clk_probe,
+ .remove_new = hisi_clk_remove,
.driver = {
.name = "hi3660-clk",
.of_match_table = hi3660_clk_match_table,
},
};
-static int __init hi3660_clk_init(void)
-{
- return platform_driver_register(&hi3660_clk_driver);
-}
-core_initcall(hi3660_clk_init);
+module_platform_driver(hi3660_clk_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("HiSilicon Hi3660 Clock Driver");
--
2.43.0
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