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Message-ID: <ZhfGf4ycvv6LcKlv@smile.fi.intel.com>
Date: Thu, 11 Apr 2024 14:16:15 +0300
From: Andy Shevchenko <andriy.shevchenko@...el.com>
To: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Jonathan Cameron <Jonathan.Cameron@...wei.com>,
	linux-pci@...r.kernel.org, Bjorn Helgaas <bhelgaas@...gle.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Wilczyński <kw@...ux.com>,
	Igor Mammedov <imammedo@...hat.com>, Lukas Wunner <lukas@...ner.de>,
	Mika Westerberg <mika.westerberg@...ux.intel.com>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	LKML <linux-kernel@...r.kernel.org>, linuxarm@...wei.com,
	linux-cxl@...r.kernel.org
Subject: Re: [PATCH v2 0/7] PCI: Solve two bridge window sizing issues

On Thu, Apr 11, 2024 at 01:41:10PM +0300, Ilpo Järvinen wrote:
> On Tue, 9 Apr 2024, Jonathan Cameron wrote:
> > On Thu, 28 Dec 2023 18:57:00 +0200
> > Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com> wrote:

..

> E.g., there are
> zero pci_dbg()s in pci_bus_distribute_available_resources(). So unless the
> window is adjusted, we have zero information on what's going on so no
> surprise why everyone is "drawing a blank". :-(

Perhaps it's a good time to start trace events / points for PCI (if not yet)?

Just my 2c.

-- 
With Best Regards,
Andy Shevchenko



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