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Message-ID: <alpine.DEB.2.22.394.2404111700280.410528@sj-4150-psse-sw-opae-dev2>
Date: Thu, 11 Apr 2024 17:04:52 -0700 (PDT)
From: matthew.gerlach@...ux.intel.com
To: Rob Herring <robh@...nel.org>
cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] dt-bindings: PCI: altera: Convert to YAML
On Wed, 10 Apr 2024, Rob Herring wrote:
> On Fri, Apr 05, 2024 at 09:53:22AM -0500, matthew.gerlach@...ux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>>
>> Convert the device tree bindings for the Altera Root Port PCIe controller
>> from text to YAML.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>> ---
>> v2:
>> - Move allOf: to bottom of file, just like example-schema is showing
>> - add constraint for reg and reg-names
>> - remove unneeded device_type
>> - drop #address-cells and #size-cells
>> - change minItems to maxItems for interrupts:
>> - change msi-parent to just "msi-parent: true"
>> - cleaned up required:
>> - make subject consistent with other commits coverting to YAML
>> - s/overt/onvert/g
>> ---
>> .../devicetree/bindings/pci/altera-pcie.txt | 50 ---------
>> .../bindings/pci/altr,pcie-root-port.yaml | 106 ++++++++++++++++++
>> 2 files changed, 106 insertions(+), 50 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt
>> create mode 100644 Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
>> deleted file mode 100644
>> index 816b244a221e..000000000000
>> --- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
>> +++ /dev/null
>> @@ -1,50 +0,0 @@
>> -* Altera PCIe controller
>> -
>> -Required properties:
>> -- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
>> -- reg: a list of physical base address and length for TXS and CRA.
>> - For "altr,pcie-root-port-2.0", additional HIP base address and length.
>> -- reg-names: must include the following entries:
>> - "Txs": TX slave port region
>> - "Cra": Control register access region
>> - "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
>> -- interrupts: specifies the interrupt source of the parent interrupt
>> - controller. The format of the interrupt specifier depends
>> - on the parent interrupt controller.
>> -- device_type: must be "pci"
>> -- #address-cells: set to <3>
>> -- #size-cells: set to <2>
>> -- #interrupt-cells: set to <1>
>> -- ranges: describes the translation of addresses for root ports and
>> - standard PCI regions.
>> -- interrupt-map-mask and interrupt-map: standard PCI properties to define the
>> - mapping of the PCIe interface to interrupt numbers.
>> -
>> -Optional properties:
>> -- msi-parent: Link to the hardware entity that serves as the MSI controller
>> - for this PCIe controller.
>> -- bus-range: PCI bus numbers covered
>> -
>> -Example
>> - pcie_0: pcie@...000000 {
>> - compatible = "altr,pcie-root-port-1.0";
>> - reg = <0xc0000000 0x20000000>,
>> - <0xff220000 0x00004000>;
>> - reg-names = "Txs", "Cra";
>> - interrupt-parent = <&hps_0_arm_gic_0>;
>> - interrupts = <0 40 4>;
>> - interrupt-controller;
>> - #interrupt-cells = <1>;
>> - bus-range = <0x0 0xFF>;
>> - device_type = "pci";
>> - msi-parent = <&msi_to_gic_gen_0>;
>> - #address-cells = <3>;
>> - #size-cells = <2>;
>> - interrupt-map-mask = <0 0 0 7>;
>> - interrupt-map = <0 0 0 1 &pcie_0 1>,
>> - <0 0 0 2 &pcie_0 2>,
>> - <0 0 0 3 &pcie_0 3>,
>> - <0 0 0 4 &pcie_0 4>;
>> - ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
>> - 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
>> - };
>> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> new file mode 100644
>> index 000000000000..999dcda05f55
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
>> @@ -0,0 +1,106 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright (C) 2024, Intel Corporation
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Altera PCIe Root Port
>> +
>> +maintainers:
>> + - Matthew Gerlach <matthew.gerlach@...ux.intel.com>
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - enum:
>> + - altr,pcie-root-port-1.0
>> + - altr,pcie-root-port-2.0
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupt-map-mask:
>> + items:
>> + - const: 0
>> + - const: 0
>> + - const: 0
>> + - const: 7
>> +
>> + interrupt-map:
>> + maxItems: 4
>> +
>> + "#interrupt-cells":
>> + const: 1
>
> Already defined in the common schema, drop.
When I remove the lines above, "make dt_binding_check" gives me the
warning, properties: '#interrupt-cells' is a dependency of 'interrupt-map'.
>
>> +
>> + msi-parent: true
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - device_type
>
> Drop.
I will drop this in v3.
>
>> + - interrupts
>> + - interrupt-map
>> + - interrupt-map-mask
>> +
>> +unevaluatedProperties: false
>> +
>> +allOf:
>> + - $ref: /schemas/pci/pci-bus.yaml#
>> + - if:
>> + properties:
>> + compatible:
>> + enum:
>> + - altr,pcie-root-port-1.0
>> + then:
>> + properties:
>> + reg:
>> + items:
>> + - description: TX slave port region
>> + - description: Control register access region
>> +
>> + reg-names:
>> + items:
>> + - const: Txs
>> + - const: Cra
>> +
>> + else:
>> + properties:
>> + reg:
>> + items:
>> + - description: Hard IP region
>> + - description: TX slave port region
>> + - description: Control register access region
>> +
>> + reg-names:
>> + items:
>> + - const: Hip
>> + - const: Txs
>> + - const: Cra
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interrupt-controller/irq.h>
>> + pcie_0: pcie@...000000 {
>> + compatible = "altr,pcie-root-port-1.0";
>> + reg = <0xc0000000 0x20000000>,
>> + <0xff220000 0x00004000>;
>> + reg-names = "Txs", "Cra";
>> + interrupt-parent = <&hps_0_arm_gic_0>;
>> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
>> + #interrupt-cells = <1>;
>> + bus-range = <0x0 0xff>;
>> + device_type = "pci";
>> + msi-parent = <&msi_to_gic_gen_0>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + interrupt-map-mask = <0 0 0 7>;
>> + interrupt-map = <0 0 0 1 &pcie_intc 1>,
>> + <0 0 0 2 &pcie_intc 2>,
>> + <0 0 0 3 &pcie_intc 3>,
>> + <0 0 0 4 &pcie_intc 4>;
>> + ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
>> + 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
>> + };
>> --
>> 2.34.1
>>
>
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