| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <3111e684-249e-42f9-9105-f62700fe9959@ti.com>
Date: Fri, 12 Apr 2024 09:51:48 +0530
From: Neha Malcom Francis <n-francis@...com>
To: "Kumar, Udit" <u-kumar1@...com>, <robh@...nel.org>, <conor+dt@...nel.org>,
<krzysztof.kozlowski+dt@...aro.org>, <vigneshr@...com>, <nm@...com>
CC: <linux-arm-kernel@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <kristo@...nel.org>
Subject: Re: [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add the MAIN domain
watchdog instances
Hi Udit
On 10/04/24 11:06, Kumar, Udit wrote:
> Hi Neha
>
> On 3/26/2024 5:57 PM, Neha Malcom Francis wrote:
>> There are 10 watchdog instances in the MAIN domain:
>> * one each for the 2 A72 cores
>> * one for the GPU core
>> * one for the C7x core
>> * one each for the 2 C66x cores
>> * one each for the 4 R5F cores
>>
>> Currently, the devicetree only describes watchdog instances for the A72
>> cores and enables them. Describe the remaining but reserve them as they
>> will be used by their respective firmware.
>>
>> Signed-off-by: Neha Malcom Francis <n-francis@...com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 93 +++++++++++++++++++++++
>> 1 file changed, 93 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index c7eafbc862f9..d8930b8ea8ec 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -2157,6 +2157,99 @@ watchdog1: watchdog@...0000 {
>> assigned-clock-parents = <&k3_clks 253 5>;
>> };
>
> Looking at TRM, SPRUIJ7*3–December 2018–Revised March 2019,
>
> Table 12-22646. RTI Instances, says There is gap in numbering
>
> RTI0, RTI1, RTI15 and so on
>
> IMO, labels for watchdog should be as per TRM.
>
> eg watchdog2 to watchdog15, But I don't have strong opinion on either .
>
> Let maintainer suggest on this
>
>
>
>> + /*
>> + * The following RTI instances are coupled with MCU R5Fs, c7x and
>> + * GPU so keeping them reserved as these will be used by their
>> + * respective firmware
>> + */
>> + watchdog2: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x22f0000 0x00 0x100>;
>> + clocks = <&k3_clks 257 1>;
>> + power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 257 1>;
>> + assigned-clock-parents = <&k3_clks 257 5>;
>> + /* reserved for GPU */
>> + status = "reserved";
>> + };
>
> Please help me to understand, where from you got it for GPU,
>
> May be I am looking at wrong data, Again above TRM
>
> Table 12-22645. RTI Hardware Requests. RTI-15 says esm0
>
>> +
>> + watchdog3: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2300000 0x00 0x100>;
>> + clocks = <&k3_clks 256 1>;
>> + power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 256 1>;
>> + assigned-clock-parents = <&k3_clks 256 5>;
>> + /* reserved for C7X */
>> + status = "reserved";
>
> This I see in above table for Compute Cluster
>
>
>> + };
>> +
>> + watchdog4: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2380000 0x00 0x100>;
>> + clocks = <&k3_clks 254 1>;
>> + power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 254 1>;
>> + assigned-clock-parents = <&k3_clks 254 5>;
>> + /* reserved for C66X_0 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog5: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x2390000 0x00 0x100>;
>> + clocks = <&k3_clks 255 1>;
>> + power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 255 1>;
>> + assigned-clock-parents = <&k3_clks 255 5>;
>> + /* reserved for C66X_1 */
>> + status = "reserved";
>> + };
>> +
>> + watchdog6: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23c0000 0x00 0x100>;
>> + clocks = <&k3_clks 258 1>;
>> + power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 258 1>;
>> + assigned-clock-parents = <&k3_clks 258 5>;
>> + /* reserved for MAIN_R5F0_0 */
>
> TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
>
> Suggest , if split is done at fw level
>
>> + status = "reserved";
>> + };
>> +
>> + watchdog7: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23d0000 0x00 0x100>;
>> + clocks = <&k3_clks 259 1>;
>> + power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 259 1>;
>> + assigned-clock-parents = <&k3_clks 259 5>;
>> + /* reserved for MAIN_R5F0_1 */
>> + status = "reserved";
>
> TRM says, this covers both MAIN_R5F0_0 and MAIN_R5F0_1.
>
> Suggest , if split is done at fw level
>
>> + };
>> +
>> + watchdog8: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23e0000 0x00 0x100>;
>> + clocks = <&k3_clks 260 1>;
>> + power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 260 1>;
>> + assigned-clock-parents = <&k3_clks 260 5>;
>> + /* reserved for MAIN_R5F1_0 */
>> + status = "reserved";
>> + };
>
>
> TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
>
> Suggest , if split is done at fw level
>
>> +
>> + watchdog9: watchdog@...0000 {
>> + compatible = "ti,j7-rti-wdt";
>> + reg = <0x00 0x23f0000 0x00 0x100>;
>> + clocks = <&k3_clks 261 1>;
>> + power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>;
>> + assigned-clocks = <&k3_clks 261 1>;
>> + assigned-clock-parents = <&k3_clks 261 5>;
>> + /* reserved for MAIN_R5F1_1 */
>
> TRM says, this covers both MAIN_R5F1_0 and MAIN_R5F1_1.
>
> Suggest , if split is done at fw level
>
>> + status = "reserved";
>> + };
>> +
>> main_r5fss0: r5fss@...0000 {
>> compatible = "ti,j721e-r5fss";
>> ti,cluster-mode = <1>;
At firmware level, the MAIN R5s are set to split mode.
--
Thanking You
Neha Malcom Francis
Powered by blists - more mailing lists