linux-kernel - Re: [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid

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Date: Fri, 12 Apr 2024 10:57:21 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Charlie Jenkins <charlie@...osinc.com>
CC: Conor Dooley <conor@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof
 Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Paul Walmsley
	<paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou
	<aou@...s.berkeley.edu>, Guo Ren <guoren@...nel.org>, Conor Dooley
	<conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>, Jernej Skrabec
	<jernej.skrabec@...il.com>, Samuel Holland <samuel@...lland.org>, Evan Green
	<evan@...osinc.com>, Clément Léger
	<cleger@...osinc.com>, Jonathan Corbet <corbet@....net>, Shuah Khan
	<shuah@...nel.org>, <linux-riscv@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>, Palmer Dabbelt
	<palmer@...osinc.com>, <linux-arm-kernel@...ts.infradead.org>,
	<linux-sunxi@...ts.linux.dev>, <linux-doc@...r.kernel.org>,
	<linux-kselftest@...r.kernel.org>
Subject: Re: [PATCH 01/19] dt-bindings: riscv: Add vendorid and archid

On Thu, Apr 11, 2024 at 09:11:07PM -0700, Charlie Jenkins wrote:
> vendorid and marchid are required during devicetree parsing to determine
> known hardware capabilities. This parsing happens before the whole
> system has booted, so only the boot hart is online and able to report
> the value of its vendorid and archid.

I'll comment on the kernel patch, but this is not needed.

> Signed-off-by: Charlie Jenkins <charlie@...osinc.com>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d87dd50f1a4b..c21d7374636c 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -94,6 +94,17 @@ properties:
>      description:
>        The blocksize in bytes for the Zicboz cache operations.
>  
> +  riscv,vendorid:
> +    $ref: /schemas/types.yaml#/definitions/uint64
> +    description:
> +      Same value as the mvendorid CSR.
> +
> +  riscv,archid:
> +    $ref: /schemas/types.yaml#/definitions/uint64
> +    description:
> +      Same value as the marchid CSR.
> +
> +
>    # RISC-V has multiple properties for cache op block sizes as the sizes
>    # differ between individual CBO extensions
>    cache-op-block-size: false
> 
> -- 
> 2.44.0
> 

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