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Message-ID: <20240412130540.28447-2-sumitg@nvidia.com>
Date: Fri, 12 Apr 2024 18:35:39 +0530
From: Sumit Gupta <sumitg@...dia.com>
To: <krzysztof.kozlowski@...aro.org>, <robh@...nel.org>,
<conor+dt@...nel.org>, <maz@...nel.org>, <mark.rutland@....com>,
<treding@...dia.com>, <jonathanh@...dia.com>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <amhetre@...dia.com>, <bbasu@...dia.com>,
<sumitg@...dia.com>
Subject: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
MC SID and Broadbast channel register access is restricted for Guest VM.
Make both the regions as optional for SoC's from Tegra186 onwards.
Tegra MC driver will skip access to the restricted registers from Guest
if the respective regions are not present in the memory-controller node
of Guest DT.
Suggested-by: Thierry Reding <treding@...dia.com>
Signed-off-by: Sumit Gupta <sumitg@...dia.com>
---
.../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
1 file changed, 49 insertions(+), 46 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 935d63d181d9..e0bd013ecca3 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -34,11 +34,11 @@ properties:
- nvidia,tegra234-mc
reg:
- minItems: 6
+ minItems: 4
maxItems: 18
reg-names:
- minItems: 6
+ minItems: 4
maxItems: 18
interrupts:
@@ -151,12 +151,13 @@ allOf:
reg-names:
items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
+ enum:
+ - sid
+ - broadcast
+ - ch0
+ - ch1
+ - ch2
+ - ch3
- if:
properties:
@@ -165,29 +166,30 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
- - const: ch4
- - const: ch5
- - const: ch6
- - const: ch7
- - const: ch8
- - const: ch9
- - const: ch10
- - const: ch11
- - const: ch12
- - const: ch13
- - const: ch14
- - const: ch15
+ enum:
+ - sid
+ - broadcast
+ - ch0
+ - ch1
+ - ch2
+ - ch3
+ - ch4
+ - ch5
+ - ch6
+ - ch7
+ - ch8
+ - ch9
+ - ch10
+ - ch11
+ - ch12
+ - ch13
+ - ch14
+ - ch15
- if:
properties:
@@ -196,29 +198,30 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
- - const: ch4
- - const: ch5
- - const: ch6
- - const: ch7
- - const: ch8
- - const: ch9
- - const: ch10
- - const: ch11
- - const: ch12
- - const: ch13
- - const: ch14
- - const: ch15
+ enum:
+ - sid
+ - broadcast
+ - ch0
+ - ch1
+ - ch2
+ - ch3
+ - ch4
+ - ch5
+ - ch6
+ - ch7
+ - ch8
+ - ch9
+ - ch10
+ - ch11
+ - ch12
+ - ch13
+ - ch14
+ - ch15
additionalProperties: false
--
2.17.1
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