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Message-ID: <d27e38838320673b6d644a17af068a1978fd2f8b.camel@mediatek.com>
Date: Sat, 13 Apr 2024 07:21:05 +0000
From: Zhi Mao (毛智) <zhi.mao@...iatek.com>
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Subject: Re: [PATCH v3 2/2] media: i2c: Add GC05A2 image sensor driver
loop in Gcoreinc Sensor FAE: Tina
Hi Kieran,
About the gc05a2 sensor registers comments those you mentioned, please
check the the vendor's feedback.
BTW, attachment is the data sheet of this sensor, FYI.
On Sun, 2024-04-07 at 10:08 +0100, Kieran Bingham wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> Hello,
>
> Thanks for helping extending the kernels sensor driver support.
>
> My comments below can likely be taken with a pinch of salt, as they
> are
> mostly around the tabled register values ... but we have many drivers
> which are binary blobs of sensor register values and I think it would
> be
> far more beneficial to clean these up where possible...
>
> So the first question is ... Can we ?
>
>
>
> Quoting Zhi Mao (2024-04-03 04:38:25)
> > Add a V4L2 sub-device driver for Galaxycore GC05A2 image sensor.
> >
> > Signed-off-by: Zhi Mao <zhi.mao@...iatek.com>
> > ---
> > drivers/media/i2c/Kconfig | 10 +
> > drivers/media/i2c/Makefile | 1 +
> > drivers/media/i2c/gc05a2.c | 1383
> ++++++++++++++++++++++++++++++++++++
> > 3 files changed, 1394 insertions(+)
> > create mode 100644 drivers/media/i2c/gc05a2.c
> >
> > diff --git a/drivers/media/i2c/gc05a2.c
> b/drivers/media/i2c/gc05a2.c
> > new file mode 100644
> > index 000000000000..461d33055a3b
> > --- /dev/null
> > +++ b/drivers/media/i2c/gc05a2.c
> > @@ -0,0 +1,1383 @@
>
> > ...
> > +
> > +static const struct cci_reg_sequence mode_2592x1944[] = {
> > + /* system */
> > + { CCI_REG8(0x0135), 0x01 },
> > +
> > + /* pre_setting */
> > + { CCI_REG8(0x0084), 0x21 },
> > + { CCI_REG8(0x0d05), 0xcc },
> > + { CCI_REG8(0x0218), 0x00 },
> > + { CCI_REG8(0x005e), 0x48 },
> > + { CCI_REG8(0x0d06), 0x01 },
> > + { CCI_REG8(0x0007), 0x16 },
> > + { CCI_REG8(0x0101), 0x00 },
> > +
> > + /* analog */
> > + { CCI_REG8(0x0342), 0x07 },
> > + { CCI_REG8(0x0343), 0x28 },
> > + { CCI_REG8(0x0220), 0x07 },
> > + { CCI_REG8(0x0221), 0xd0 },
> > + { CCI_REG8(0x0202), 0x07 },
> > + { CCI_REG8(0x0203), 0x32 },
> > + { CCI_REG8(0x0340), 0x07 },
> > + { CCI_REG8(0x0341), 0xf0 },
> > + { CCI_REG8(0x0219), 0x00 },
> > + { CCI_REG8(0x0346), 0x00 },
> > + { CCI_REG8(0x0347), 0x04 },
> > + { CCI_REG8(0x0d14), 0x00 },
> > + { CCI_REG8(0x0d13), 0x05 },
> > + { CCI_REG8(0x0d16), 0x05 },
> > + { CCI_REG8(0x0d15), 0x1d },
> > + { CCI_REG8(0x00c0), 0x0a },
> > + { CCI_REG8(0x00c1), 0x30 },
> > + { CCI_REG8(0x034a), 0x07 },
> > + { CCI_REG8(0x034b), 0xa8 },
> > + { CCI_REG8(0x0e0a), 0x00 },
> > + { CCI_REG8(0x0e0b), 0x00 },
> > + { CCI_REG8(0x0e0e), 0x03 },
> > + { CCI_REG8(0x0e0f), 0x00 },
> > + { CCI_REG8(0x0e06), 0x0a },
> > + { CCI_REG8(0x0e23), 0x15 },
> > + { CCI_REG8(0x0e24), 0x15 },
> > + { CCI_REG8(0x0e2a), 0x10 },
> > + { CCI_REG8(0x0e2b), 0x10 },
> > + { CCI_REG8(0x0e17), 0x49 },
> > + { CCI_REG8(0x0e1b), 0x1c },
> > + { CCI_REG8(0x0e3a), 0x36 },
> > + { CCI_REG8(0x0d11), 0x84 },
> > + { CCI_REG8(0x0e52), 0x14 },
> > + { CCI_REG8(0x000b), 0x10 },
> > + { CCI_REG8(0x0008), 0x08 },
> > + { CCI_REG8(0x0223), 0x17 },
> > + { CCI_REG8(0x0d27), 0x39 },
> > + { CCI_REG8(0x0d22), 0x00 },
> > + { CCI_REG8(0x03f6), 0x0d },
> > + { CCI_REG8(0x0d04), 0x07 },
> > + { CCI_REG8(0x03f3), 0x72 },
> > + { CCI_REG8(0x03f4), 0xb8 },
> > + { CCI_REG8(0x03f5), 0xbc },
> > + { CCI_REG8(0x0d02), 0x73 },
> > +
> > + /* auto load start */
> > + { CCI_REG8(0x00cb), 0x00 },
> > +
> > + /* OUT 2592*1944 */
> > + { CCI_REG8(0x0350), 0x01 },
> > + { CCI_REG8(0x0353), 0x00 },
> > + { CCI_REG8(0x0354), 0x08 },
>
> > + { CCI_REG8(0x034c), 0x0a },
> > + { CCI_REG8(0x034d), 0x20 },
>
> Should/Could this be
> { CCI_REG16(0x034c), 2592 }, /* Width */
>
[GC05A2 FAE]: yes, we can.
>
> > + { CCI_REG8(0x021f), 0x14 },
> > +
> > + /* MIPI */
> > + { CCI_REG8(0x0107), 0x05 },
> > + { CCI_REG8(0x0117), 0x01 },
> > + { CCI_REG8(0x0d81), 0x00 },
> > + { CCI_REG8(0x0d84), 0x0c },
> > + { CCI_REG8(0x0d85), 0xa8 },
> > + { CCI_REG8(0x0d86), 0x06 },
> > + { CCI_REG8(0x0d87), 0x55 },
> > + { CCI_REG8(0x0db3), 0x06 },
> > + { CCI_REG8(0x0db4), 0x08 },
> > + { CCI_REG8(0x0db5), 0x1e },
> > + { CCI_REG8(0x0db6), 0x02 },
> > + { CCI_REG8(0x0db8), 0x12 },
> > + { CCI_REG8(0x0db9), 0x0a },
> > + { CCI_REG8(0x0d93), 0x06 },
> > + { CCI_REG8(0x0d94), 0x09 },
> > + { CCI_REG8(0x0d95), 0x0d },
> > + { CCI_REG8(0x0d99), 0x0b },
> > + { CCI_REG8(0x0084), 0x01 },
> > +
> > + /* OUT */
> > + { CCI_REG8(0x0110), 0x01 },
> > +};
> > +
> > +static const struct cci_reg_sequence mode_1280x720[] = {
> > + /* system */
> > + { CCI_REG8(0x0135), 0x05 },
>
> In 2592x1944 this is 0x01. Do you have a datasheet? Can you explain
> why
> they are different? Can you add register definitions that have names
> to
> make this more maintainable or extendable in the future?
>
> There's discussion in the recent series improving the IMX258 which
> makes
> me wonder if we should try harder to have sensor drivers with clearer
> definitions.
>
[GC05A2 FAE]: This is the difference in initialization of the sensor's
internal register settings between different modes.
we are sorry we can 's supply more informations about them.
Some register settings(such as:0x00135...) are not open for customer
modify, so there is no description for them in data sheet.
>
> > +
> > + /*pre_setting*/
>
> /* pre_setting */ ?
[GC05A2 FAE]: This remark can be removed.
>
> > + { CCI_REG8(0x0084), 0x21 },
> > + { CCI_REG8(0x0d05), 0xcc },
> > + { CCI_REG8(0x0218), 0x80 },
> > + { CCI_REG8(0x005e), 0x49 },
> > + { CCI_REG8(0x0d06), 0x81 },
> > + { CCI_REG8(0x0007), 0x16 },
> > + { CCI_REG8(0x0101), 0x00 },
>
> In 2592x1944, only register 0x0218 differs. Why? What is that? Can it
> be
> broken out to a function that applies the correct configuration at
> startuup based on a parameter instead of duplicating this table set?
>
[GC05A2 FAE]: This section is not only 0x0218 registers.
The initialization of the sensor with different graph sizes is
different. As these registers have strict programing sequece, we can
not move them to another stage.
> > +
> > + /* analog */
> > + { CCI_REG8(0x0342), 0x07 },
> > + { CCI_REG8(0x0343), 0x10 },
> > + { CCI_REG8(0x0220), 0x07 },
> > + { CCI_REG8(0x0221), 0xd0 },
> > + { CCI_REG8(0x0202), 0x03 },
> > + { CCI_REG8(0x0203), 0x32 },
> > + { CCI_REG8(0x0340), 0x04 },
> > + { CCI_REG8(0x0341), 0x08 },
> > + { CCI_REG8(0x0219), 0x00 },
> > + { CCI_REG8(0x0346), 0x01 },
> > + { CCI_REG8(0x0347), 0x00 },
> > + { CCI_REG8(0x0d14), 0x00 },
> > + { CCI_REG8(0x0d13), 0x05 },
> > + { CCI_REG8(0x0d16), 0x05 },
> > + { CCI_REG8(0x0d15), 0x1d },
> > + { CCI_REG8(0x00c0), 0x0a },
> > + { CCI_REG8(0x00c1), 0x30 },
> > + { CCI_REG8(0x034a), 0x05 },
> > + { CCI_REG8(0x034b), 0xb0 },
> > + { CCI_REG8(0x0e0a), 0x00 },
> > + { CCI_REG8(0x0e0b), 0x00 },
> > + { CCI_REG8(0x0e0e), 0x03 },
> > + { CCI_REG8(0x0e0f), 0x00 },
> > + { CCI_REG8(0x0e06), 0x0a },
> > + { CCI_REG8(0x0e23), 0x15 },
> > + { CCI_REG8(0x0e24), 0x15 },
> > + { CCI_REG8(0x0e2a), 0x10 },
> > + { CCI_REG8(0x0e2b), 0x10 },
> > + { CCI_REG8(0x0e17), 0x49 },
> > + { CCI_REG8(0x0e1b), 0x1c },
> > + { CCI_REG8(0x0e3a), 0x36 },
> > + { CCI_REG8(0x0d11), 0x84 },
> > + { CCI_REG8(0x0e52), 0x14 },
> > + { CCI_REG8(0x000b), 0x0e },
> > + { CCI_REG8(0x0008), 0x03 },
> > + { CCI_REG8(0x0223), 0x16 },
> > + { CCI_REG8(0x0d27), 0x39 },
> > + { CCI_REG8(0x0d22), 0x00 },
> > + { CCI_REG8(0x03f6), 0x0d },
> > + { CCI_REG8(0x0d04), 0x07 },
> > + { CCI_REG8(0x03f3), 0x72 },
> > + { CCI_REG8(0x03f4), 0xb8 },
> > + { CCI_REG8(0x03f5), 0xbc },
> > + { CCI_REG8(0x0d02), 0x73 },
> > +
>
> Are any of those able to be broken out to named register to be more
> clear in their intent?
>
> > + /* auto load start */
> > + { CCI_REG8(0x00cb), 0xfc },
> > +
>
> Why is this auto load start so different to the other modes 'auto
> load
> start'? What do the bits refer to ?
[GC05A2 FAE]: This is normal, it's the initialization process for each
mode.
>
> > + /* OUT 1280x720 */
> > + { CCI_REG8(0x0350), 0x01 },
> > + { CCI_REG8(0x0353), 0x00 },
> > + { CCI_REG8(0x0354), 0x0c },
>
> > + { CCI_REG8(0x034c), 0x05 },
> > + { CCI_REG8(0x034d), 0x00 },
>
> Should/Could this be
> { CCI_REG16(0x034c), 1280 },
>
> Are there any other register settings that would make more sense to
> be
> in decimal units that match their actual context?
>
[GC05A2 FAE]: It's coding style issue.
>
> > + { CCI_REG8(0x021f), 0x14 },
>
> I don't see a setting for 720/0x2d0. Do these registers only set the
> width?
>
[GC05A2 FAE]: This is the characteristic of GC05a2 sensor. Filling the
width and height will be calculated automatically.
> > +
> > + /* MIPI */
> > + { CCI_REG8(0x0107), 0x05 },
> > + { CCI_REG8(0x0117), 0x01 },
> > + { CCI_REG8(0x0d81), 0x00 },
> > + { CCI_REG8(0x0d84), 0x06 },
> > + { CCI_REG8(0x0d85), 0x40 },
> > + { CCI_REG8(0x0d86), 0x03 },
> > + { CCI_REG8(0x0d87), 0x21 },
> > + { CCI_REG8(0x0db3), 0x03 },
> > + { CCI_REG8(0x0db4), 0x04 },
> > + { CCI_REG8(0x0db5), 0x0d },
> > + { CCI_REG8(0x0db6), 0x01 },
> > + { CCI_REG8(0x0db8), 0x04 },
> > + { CCI_REG8(0x0db9), 0x06 },
> > + { CCI_REG8(0x0d93), 0x03 },
> > + { CCI_REG8(0x0d94), 0x04 },
> > + { CCI_REG8(0x0d95), 0x05 },
> > + { CCI_REG8(0x0d99), 0x06 },
> > + { CCI_REG8(0x0084), 0x01 },
> > +
> > + /* OUT */
>
> Out where? What is out?
>
[GC05A2 FAE]: It means the sensor starts to output data.
> > + { CCI_REG8(0x0110), 0x01 },
> > +};
> > +
> > +static const struct cci_reg_sequence mode_table_common[] = {
> > + { GC05A2_STREAMING_REG, 0x00 },
> > + /* system */
> > + { CCI_REG8(0x0315), 0xd4 },
> > + { CCI_REG8(0x0d06), 0x01 },
> > + { CCI_REG8(0x0a70), 0x80 },
> > + { CCI_REG8(0x031a), 0x00 },
> > + { CCI_REG8(0x0314), 0x00 },
> > + { CCI_REG8(0x0130), 0x08 },
> > + { CCI_REG8(0x0132), 0x01 },
> > + { CCI_REG8(0x0136), 0x38 },
> > + { CCI_REG8(0x0137), 0x03 },
> > + { CCI_REG8(0x0134), 0x5b },
> > + { CCI_REG8(0x031c), 0xe0 },
> > + { CCI_REG8(0x0d82), 0x14 },
> > + { CCI_REG8(0x0dd1), 0x56 },
> > +
> > + /* gate_mode */
> > + { CCI_REG8(0x0af4), 0x01 },
> > + { CCI_REG8(0x0002), 0x10 },
> > + { CCI_REG8(0x00c3), 0x34 },
> > +
> > + /* auto load start */
>
> The previous 'auto load start' referenced 0x00cb ?
[GC05A2 FAE]: Here is the initialization process for each mode, when
programe the settings with different sizes, we need to init and call
these mode settings.
>
> > + { CCI_REG8(0x00c4), 0x00 },
> > + { CCI_REG8(0x00c5), 0x01 },
> > + { CCI_REG8(0x0af6), 0x00 },
> > + { CCI_REG8(0x0ba0), 0x17 },
> > + { CCI_REG8(0x0ba1), 0x00 },
> > + { CCI_REG8(0x0ba2), 0x00 },
> > + { CCI_REG8(0x0ba3), 0x00 },
> > + { CCI_REG8(0x0ba4), 0x03 },
> > + { CCI_REG8(0x0ba5), 0x00 },
> > + { CCI_REG8(0x0ba6), 0x00 },
> > + { CCI_REG8(0x0ba7), 0x00 },
> > + { CCI_REG8(0x0ba8), 0x40 },
> > + { CCI_REG8(0x0ba9), 0x00 },
> > + { CCI_REG8(0x0baa), 0x00 },
> > + { CCI_REG8(0x0bab), 0x00 },
> > + { CCI_REG8(0x0bac), 0x40 },
> > + { CCI_REG8(0x0bad), 0x00 },
> > + { CCI_REG8(0x0bae), 0x00 },
> > + { CCI_REG8(0x0baf), 0x00 },
> > + { CCI_REG8(0x0bb0), 0x02 },
> > + { CCI_REG8(0x0bb1), 0x00 },
> > + { CCI_REG8(0x0bb2), 0x00 },
> > + { CCI_REG8(0x0bb3), 0x00 },
> > + { CCI_REG8(0x0bb8), 0x02 },
> > + { CCI_REG8(0x0bb9), 0x00 },
> > + { CCI_REG8(0x0bba), 0x00 },
> > + { CCI_REG8(0x0bbb), 0x00 },
> > + { CCI_REG8(0x0a70), 0x80 },
> > + { CCI_REG8(0x0a71), 0x00 },
> > + { CCI_REG8(0x0a72), 0x00 },
> > + { CCI_REG8(0x0a66), 0x00 },
> > + { CCI_REG8(0x0a67), 0x80 },
> > + { CCI_REG8(0x0a4d), 0x4e },
> > + { CCI_REG8(0x0a50), 0x00 },
> > + { CCI_REG8(0x0a4f), 0x0c },
> > + { CCI_REG8(0x0a66), 0x00 },
> > + { CCI_REG8(0x00ca), 0x00 },
> > + { CCI_REG8(0x00cc), 0x00 },
> > + { CCI_REG8(0x00cd), 0x00 },
> > + { CCI_REG8(0x0aa1), 0x00 },
> > + { CCI_REG8(0x0aa2), 0xe0 },
> > + { CCI_REG8(0x0aa3), 0x00 },
> > + { CCI_REG8(0x0aa4), 0x40 },
> > + { CCI_REG8(0x0a90), 0x03 },
> > + { CCI_REG8(0x0a91), 0x0e },
> > + { CCI_REG8(0x0a94), 0x80 },
> > +
> > + /* standby */
> > + { CCI_REG8(0x0af6), 0x20 },
> > + { CCI_REG8(0x0b00), 0x91 },
> > + { CCI_REG8(0x0b01), 0x17 },
> > + { CCI_REG8(0x0b02), 0x01 },
> > + { CCI_REG8(0x0b03), 0x00 },
> > + { CCI_REG8(0x0b04), 0x01 },
> > + { CCI_REG8(0x0b05), 0x17 },
> > + { CCI_REG8(0x0b06), 0x01 },
> > + { CCI_REG8(0x0b07), 0x00 },
> > + { CCI_REG8(0x0ae9), 0x01 },
> > + { CCI_REG8(0x0aea), 0x02 },
> > + { CCI_REG8(0x0ae8), 0x53 },
> > + { CCI_REG8(0x0ae8), 0x43 },
> > +
> > + /* gain_partition */
> > + { CCI_REG8(0x0af6), 0x30 },
> > + { CCI_REG8(0x0b00), 0x08 },
> > + { CCI_REG8(0x0b01), 0x0f },
> > + { CCI_REG8(0x0b02), 0x00 },
> > + { CCI_REG8(0x0b04), 0x1c },
> > + { CCI_REG8(0x0b05), 0x24 },
> > + { CCI_REG8(0x0b06), 0x00 },
> > + { CCI_REG8(0x0b08), 0x30 },
> > + { CCI_REG8(0x0b09), 0x40 },
> > + { CCI_REG8(0x0b0a), 0x00 },
> > + { CCI_REG8(0x0b0c), 0x0e },
> > + { CCI_REG8(0x0b0d), 0x2a },
> > + { CCI_REG8(0x0b0e), 0x00 },
> > + { CCI_REG8(0x0b10), 0x0e },
> > + { CCI_REG8(0x0b11), 0x2b },
> > + { CCI_REG8(0x0b12), 0x00 },
> > + { CCI_REG8(0x0b14), 0x0e },
> > + { CCI_REG8(0x0b15), 0x23 },
> > + { CCI_REG8(0x0b16), 0x00 },
> > + { CCI_REG8(0x0b18), 0x0e },
> > + { CCI_REG8(0x0b19), 0x24 },
> > + { CCI_REG8(0x0b1a), 0x00 },
> > + { CCI_REG8(0x0b1c), 0x0c },
> > + { CCI_REG8(0x0b1d), 0x0c },
> > + { CCI_REG8(0x0b1e), 0x00 },
> > + { CCI_REG8(0x0b20), 0x03 },
> > + { CCI_REG8(0x0b21), 0x03 },
> > + { CCI_REG8(0x0b22), 0x00 },
> > + { CCI_REG8(0x0b24), 0x0e },
> > + { CCI_REG8(0x0b25), 0x0e },
> > + { CCI_REG8(0x0b26), 0x00 },
> > + { CCI_REG8(0x0b28), 0x03 },
> > + { CCI_REG8(0x0b29), 0x03 },
> > + { CCI_REG8(0x0b2a), 0x00 },
> > + { CCI_REG8(0x0b2c), 0x12 },
> > + { CCI_REG8(0x0b2d), 0x12 },
> > + { CCI_REG8(0x0b2e), 0x00 },
> > + { CCI_REG8(0x0b30), 0x08 },
> > + { CCI_REG8(0x0b31), 0x08 },
> > + { CCI_REG8(0x0b32), 0x00 },
> > + { CCI_REG8(0x0b34), 0x14 },
> > + { CCI_REG8(0x0b35), 0x14 },
> > + { CCI_REG8(0x0b36), 0x00 },
> > + { CCI_REG8(0x0b38), 0x10 },
> > + { CCI_REG8(0x0b39), 0x10 },
> > + { CCI_REG8(0x0b3a), 0x00 },
> > + { CCI_REG8(0x0b3c), 0x16 },
> > + { CCI_REG8(0x0b3d), 0x16 },
> > + { CCI_REG8(0x0b3e), 0x00 },
> > + { CCI_REG8(0x0b40), 0x10 },
> > + { CCI_REG8(0x0b41), 0x10 },
> > + { CCI_REG8(0x0b42), 0x00 },
> > + { CCI_REG8(0x0b44), 0x19 },
> > + { CCI_REG8(0x0b45), 0x19 },
> > + { CCI_REG8(0x0b46), 0x00 },
> > + { CCI_REG8(0x0b48), 0x16 },
> > + { CCI_REG8(0x0b49), 0x16 },
> > + { CCI_REG8(0x0b4a), 0x00 },
> > + { CCI_REG8(0x0b4c), 0x19 },
> > + { CCI_REG8(0x0b4d), 0x19 },
> > + { CCI_REG8(0x0b4e), 0x00 },
> > + { CCI_REG8(0x0b50), 0x16 },
> > + { CCI_REG8(0x0b51), 0x16 },
> > + { CCI_REG8(0x0b52), 0x00 },
> > + { CCI_REG8(0x0b80), 0x01 },
> > + { CCI_REG8(0x0b81), 0x00 },
> > + { CCI_REG8(0x0b82), 0x00 },
> > + { CCI_REG8(0x0b84), 0x00 },
> > + { CCI_REG8(0x0b85), 0x00 },
> > + { CCI_REG8(0x0b86), 0x00 },
> > + { CCI_REG8(0x0b88), 0x01 },
> > + { CCI_REG8(0x0b89), 0x6a },
> > + { CCI_REG8(0x0b8a), 0x00 },
> > + { CCI_REG8(0x0b8c), 0x00 },
> > + { CCI_REG8(0x0b8d), 0x01 },
> > + { CCI_REG8(0x0b8e), 0x00 },
> > + { CCI_REG8(0x0b90), 0x01 },
> > + { CCI_REG8(0x0b91), 0xf6 },
> > + { CCI_REG8(0x0b92), 0x00 },
> > + { CCI_REG8(0x0b94), 0x00 },
> > + { CCI_REG8(0x0b95), 0x02 },
> > + { CCI_REG8(0x0b96), 0x00 },
> > + { CCI_REG8(0x0b98), 0x02 },
> > + { CCI_REG8(0x0b99), 0xc4 },
> > + { CCI_REG8(0x0b9a), 0x00 },
> > + { CCI_REG8(0x0b9c), 0x00 },
> > + { CCI_REG8(0x0b9d), 0x03 },
> > + { CCI_REG8(0x0b9e), 0x00 },
> > + { CCI_REG8(0x0ba0), 0x03 },
> > + { CCI_REG8(0x0ba1), 0xd8 },
> > + { CCI_REG8(0x0ba2), 0x00 },
> > + { CCI_REG8(0x0ba4), 0x00 },
> > + { CCI_REG8(0x0ba5), 0x04 },
> > + { CCI_REG8(0x0ba6), 0x00 },
> > + { CCI_REG8(0x0ba8), 0x05 },
> > + { CCI_REG8(0x0ba9), 0x4d },
> > + { CCI_REG8(0x0baa), 0x00 },
> > + { CCI_REG8(0x0bac), 0x00 },
> > + { CCI_REG8(0x0bad), 0x05 },
> > + { CCI_REG8(0x0bae), 0x00 },
> > + { CCI_REG8(0x0bb0), 0x07 },
> > + { CCI_REG8(0x0bb1), 0x3e },
> > + { CCI_REG8(0x0bb2), 0x00 },
> > + { CCI_REG8(0x0bb4), 0x00 },
> > + { CCI_REG8(0x0bb5), 0x06 },
> > + { CCI_REG8(0x0bb6), 0x00 },
> > + { CCI_REG8(0x0bb8), 0x0a },
> > + { CCI_REG8(0x0bb9), 0x1a },
> > + { CCI_REG8(0x0bba), 0x00 },
> > + { CCI_REG8(0x0bbc), 0x09 },
> > + { CCI_REG8(0x0bbd), 0x36 },
> > + { CCI_REG8(0x0bbe), 0x00 },
> > + { CCI_REG8(0x0bc0), 0x0e },
> > + { CCI_REG8(0x0bc1), 0x66 },
> > + { CCI_REG8(0x0bc2), 0x00 },
> > + { CCI_REG8(0x0bc4), 0x10 },
> > + { CCI_REG8(0x0bc5), 0x06 },
> > + { CCI_REG8(0x0bc6), 0x00 },
> > + { CCI_REG8(0x02c1), 0xe0 },
> > + { CCI_REG8(0x0207), 0x04 },
> > + { CCI_REG8(0x02c2), 0x10 },
> > + { CCI_REG8(0x02c3), 0x74 },
> > + { CCI_REG8(0x02c5), 0x09 },
> > + { CCI_REG8(0x02c1), 0xe0 },
> > + { CCI_REG8(0x0207), 0x04 },
> > + { CCI_REG8(0x02c2), 0x10 },
> > + { CCI_REG8(0x02c5), 0x09 },
> > + { CCI_REG8(0x02c1), 0xe0 },
> > + { CCI_REG8(0x0207), 0x04 },
> > + { CCI_REG8(0x02c2), 0x10 },
> > + { CCI_REG8(0x02c5), 0x09 },
> > +
> > + /* auto load CH_GAIN */
> > + { CCI_REG8(0x0aa1), 0x15 },
> > + { CCI_REG8(0x0aa2), 0x50 },
> > + { CCI_REG8(0x0aa3), 0x00 },
> > + { CCI_REG8(0x0aa4), 0x09 },
> > + { CCI_REG8(0x0a90), 0x25 },
> > + { CCI_REG8(0x0a91), 0x0e },
> > + { CCI_REG8(0x0a94), 0x80 },
> > +
> > + /* ISP */
> > + { CCI_REG8(0x0050), 0x00 },
> > + { CCI_REG8(0x0089), 0x83 },
> > + { CCI_REG8(0x005a), 0x40 },
> > + { CCI_REG8(0x00c3), 0x35 },
> > + { CCI_REG8(0x00c4), 0x80 },
> > + { CCI_REG8(0x0080), 0x10 },
> > + { CCI_REG8(0x0040), 0x12 },
> > + { CCI_REG8(0x0053), 0x0a },
> > + { CCI_REG8(0x0054), 0x44 },
> > + { CCI_REG8(0x0055), 0x32 },
> > + { CCI_REG8(0x0058), 0x89 },
> > + { CCI_REG8(0x004a), 0x03 },
> > + { CCI_REG8(0x0048), 0xf0 },
> > + { CCI_REG8(0x0049), 0x0f },
> > + { CCI_REG8(0x0041), 0x20 },
> > + { CCI_REG8(0x0043), 0x0a },
> > + { CCI_REG8(0x009d), 0x08 },
> > + { CCI_REG8(0x0236), 0x40 },
> > +
> > + /* gain */
>
> Is the gain configurable? Is this analogue gain? digital gain? or
> colour
> balanace gains ?
>
[GC05A2 FAE]: They are sensor internal gain registers.
>
> > + { CCI_REG8(0x0204), 0x04 },
> > + { CCI_REG8(0x0205), 0x00 },
> > + { CCI_REG8(0x02b3), 0x00 },
> > + { CCI_REG8(0x02b4), 0x00 },
> > + { CCI_REG8(0x009e), 0x01 },
> > + { CCI_REG8(0x009f), 0x94 },
> > +
> > + /* auto load REG */
> > + { CCI_REG8(0x0aa1), 0x10 },
> > + { CCI_REG8(0x0aa2), 0xf8 },
> > + { CCI_REG8(0x0aa3), 0x00 },
> > + { CCI_REG8(0x0aa4), 0x1f },
> > + { CCI_REG8(0x0a90), 0x11 },
> > + { CCI_REG8(0x0a91), 0x0e },
> > + { CCI_REG8(0x0a94), 0x80 },
> > + { CCI_REG8(0x03fe), 0x00 },
> > + { CCI_REG8(0x0a90), 0x00 },
> > + { CCI_REG8(0x0a70), 0x00 },
> > + { CCI_REG8(0x0a67), 0x00 },
> > + { CCI_REG8(0x0af4), 0x29 },
> > +
> > + /* DPHY */
> > + { CCI_REG8(0x0d80), 0x07 },
> > + { CCI_REG8(0x0dd3), 0x18 },
> > +
> > + /* CISCTL_Reset */
> > + { CCI_REG8(0x031c), 0x80 },
> > + { CCI_REG8(0x03fe), 0x30 },
> > + { CCI_REG8(0x0d17), 0x06 },
> > + { CCI_REG8(0x03fe), 0x00 },
> > + { CCI_REG8(0x0d17), 0x00 },
> > + { CCI_REG8(0x031c), 0x93 },
> > + { CCI_REG8(0x03fe), 0x00 },
> > + { CCI_REG8(0x031c), 0x80 },
> > + { CCI_REG8(0x03fe), 0x30 },
> > + { CCI_REG8(0x0d17), 0x06 },
> > + { CCI_REG8(0x03fe), 0x00 },
> > + { CCI_REG8(0x0d17), 0x00 },
> > + { CCI_REG8(0x031c), 0x93 },
> > +};
> > +
>
> >
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