linux-kernel - Re: [PATCH v5 5/5] iio: adc: ad7192: Add AD7194 support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <dfa86da4-7d2d-4d7e-ac50-86d3713f44d9@gmail.com>
Date: Sun, 14 Apr 2024 23:14:28 +0300
From: Alisa-Dariana Roman <alisadariana@...il.com>
To: David Lechner <dlechner@...libre.com>
Cc: michael.hennerich@...log.com, linux-iio@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 alexandru.tachici@...log.com, lars@...afoo.de, jic23@...nel.org,
 robh@...nel.org, krzysztof.kozlowski+dt@...aro.org, conor+dt@...nel.org,
 lgirdwood@...il.com, broonie@...nel.org, andy@...nel.org,
 nuno.sa@...log.com, marcelo.schmitt@...log.com, bigunclemax@...il.com,
 okan.sahin@...log.com, fr0st61te@...il.com, alisa.roman@...log.com,
 marcus.folkesson@...il.com, schnelle@...ux.ibm.com, liambeguin@...il.com
Subject: Re: [PATCH v5 5/5] iio: adc: ad7192: Add AD7194 support

On 13.04.2024 23:05, David Lechner wrote:
> On Sat, Apr 13, 2024 at 10:13 AM Alisa-Dariana Roman
> <alisadariana@...il.com> wrote:
>>
>> Unlike the other AD719Xs, AD7194 has configurable differential
>> channels. The user can dynamically configure them in the devicetree.
>>
>> Also modify config AD7192 description for better scaling.
>>
>> Moved ad7192_chip_info struct definition to allow use of callback
>> function parse_channels().
> 
> It looks like this no longer needs to be moved in this revision.
> 
>>
>> Signed-off-by: Alisa-Dariana Roman <alisa.roman@...log.com>
>> ---
>>   drivers/iio/adc/Kconfig  |  11 ++-
>>   drivers/iio/adc/ad7192.c | 140 ++++++++++++++++++++++++++++++++++++---
>>   2 files changed, 138 insertions(+), 13 deletions(-)

..

> 
>> +       if (!ad7194_channels)
>> +               return -ENOMEM;
>> +
>> +       indio_dev->channels = ad7194_channels;
>> +       indio_dev->num_channels = num_channels;
>> +
>> +       device_for_each_child_node(dev, child) {
>> +               *ad7194_channels = ad7194_chan_diff;
>> +               ad7194_channels->scan_index = index++;
>> +               ret = ad7192_parse_channel(child, ad7194_channels);
>> +               if (ret) {
>> +                       fwnode_handle_put(child);
>> +                       return ret;
>> +               }
>> +               ad7194_channels++;
>> +       }
>> +
>> +       *ad7194_channels = ad7194_chan_temp;
>> +       ad7194_channels->scan_index = index++;
>> +       ad7194_channels->address = AD7194_CH_TEMP;
>> +       ad7194_channels++;
> 
> nit: It would seem more natural to have all voltage channels
> altogether rather than having the temperature channel in between.

I wrote the channels like this to match the other chips:

static const struct iio_chan_spec ad7193_channels[] = {
	AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
	AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
	AD7193_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
	AD7193_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
	AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
	AD7193_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M),
	AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
	AD7193_CHANNEL(7, 2, AD7193_CH_AIN2),
	AD7193_CHANNEL(8, 3, AD7193_CH_AIN3),
	AD7193_CHANNEL(9, 4, AD7193_CH_AIN4),
	AD7193_CHANNEL(10, 5, AD7193_CH_AIN5),
	AD7193_CHANNEL(11, 6, AD7193_CH_AIN6),
	AD7193_CHANNEL(12, 7, AD7193_CH_AIN7),
	AD7193_CHANNEL(13, 8, AD7193_CH_AIN8),
	IIO_CHAN_SOFT_TIMESTAMP(14),
};

Kind regards,
Alisa-Dariana Roman