linux-kernel - [PATCH] clk: sophgo: avoid open-coded 64-bit division

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date: Mon, 15 Apr 2024 15:45:20 +0200
From: Arnd Bergmann <arnd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Chen Wang <unicorn_wang@...look.com>,
	Inochi Amaoto <inochiama@...look.com>
Cc: Arnd Bergmann <arnd@...db.de>,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org
Subject: [PATCH] clk: sophgo: avoid open-coded 64-bit division

From: Arnd Bergmann <arnd@...db.de>

On 32-bit architectures, the 64-bit division leads to a link failure:

arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'

This one is not called in a fast path, and there is already another div_u64()
variant used in the same function, so convert it to div64_u64_rem().

Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Arnd Bergmann <arnd@...db.de>
---
 drivers/clk/sophgo/clk-cv18xx-pll.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c
index c546dad1791c..29e24098bf5f 100644
--- a/drivers/clk/sophgo/clk-cv18xx-pll.c
+++ b/drivers/clk/sophgo/clk-cv18xx-pll.c
@@ -205,8 +205,7 @@ static unsigned long fpll_calc_rate(unsigned long parent_rate,
 	unsigned long rate;
 
 	dividend <<= PLL_SYN_FACTOR_DOT_POS - 1;
-	rate = dividend / factor;
-	dividend %= factor;
+	rate = div64_u64_rem(dividend, factor, &dividend);
 
 	if (is_full_parent) {
 		dividend <<= 1;
-- 
2.39.2