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Message-ID: <CAA8EJprnMVSoOt7XtwcVXjFGzkPhompcfz3Zw4Hoxhk5-g5W0g@mail.gmail.com>
Date: Tue, 16 Apr 2024 21:56:05 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Ajit Pandey <quic_ajipan@...cinc.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konrad.dybcio@...aro.org>, Vinod Koul <vkoul@...nel.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@...aro.org>, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Taniya Das <quic_tdas@...cinc.com>,
Jagadeesh Kona <quic_jkona@...cinc.com>, Imran Shaik <quic_imrashai@...cinc.com>,
Satya Priya Kakitapalli <quic_skakitap@...cinc.com>
Subject: Re: [PATCH V2 3/8] clk: qcom: Add DISPCC driver support for SM4450
On Tue, 16 Apr 2024 at 21:22, Ajit Pandey <quic_ajipan@...cinc.com> wrote:
>
> Add Display Clock Controller (DISPCC) support for SM4450 platform.
>
> Signed-off-by: Ajit Pandey <quic_ajipan@...cinc.com>
> ---
> drivers/clk/qcom/Kconfig | 10 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/dispcc-sm4450.c | 781 +++++++++++++++++++++++++++++++
> 3 files changed, 792 insertions(+)
> create mode 100644 drivers/clk/qcom/dispcc-sm4450.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 8ab08e7b5b6c..9fce64ced353 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -826,6 +826,16 @@ config SM_CAMCC_8550
> Support for the camera clock controller on SM8550 devices.
> Say Y if you want to support camera devices and camera functionality.
>
> +config SM_DISPCC_4450
> + tristate "SM4450 Display Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + depends on SM_GCC_4450
> + help
> + Support for the display clock controller on Qualcomm Technologies, Inc
> + SM4450 devices.
> + Say Y if you want to support display devices and functionality such as
> + splash screen
> +
> config SM_DISPCC_6115
> tristate "SM6115 Display Clock Controller"
> depends on ARM64 || COMPILE_TEST
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index dec5b6db6860..68d1c5192c86 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -109,6 +109,7 @@ obj-$(CONFIG_SM_CAMCC_6350) += camcc-sm6350.o
> obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
> obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
> obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
> +obj-$(CONFIG_SM_DISPCC_4450) += dispcc-sm4450.o
> obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o
> obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
> obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
> diff --git a/drivers/clk/qcom/dispcc-sm4450.c b/drivers/clk/qcom/dispcc-sm4450.c
> new file mode 100644
> index 000000000000..7668b4bafae5
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc-sm4450.c
> @@ -0,0 +1,781 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/qcom,sm4450-dispcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
> +enum {
> + DT_BI_TCXO,
> + DT_BI_TCXO_AO,
> + DT_AHB_CLK,
> + DT_SLEEP_CLK,
> +
> + DT_DSI0_PHY_PLL_OUT_BYTECLK,
> + DT_DSI0_PHY_PLL_OUT_DSICLK,
> +};
> +
> +enum {
> + P_BI_TCXO,
> + P_DISP_CC_PLL0_OUT_MAIN,
> + P_DISP_CC_PLL1_OUT_EVEN,
> + P_DISP_CC_PLL1_OUT_MAIN,
> + P_DSI0_PHY_PLL_OUT_BYTECLK,
> + P_DSI0_PHY_PLL_OUT_DSICLK,
> + P_SLEEP_CLK,
> +};
> +
> +static const struct pll_vco lucid_evo_vco[] = {
> + { 249600000, 2020000000, 0 },
> +};
> +
> +/* 600.0 MHz Configuration */
> +static const struct alpha_pll_config disp_cc_pll0_config = {
> + .l = 0x1f,
> + .alpha = 0x4000,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00182261,
> + .config_ctl_hi1_val = 0x32aa299c,
> + .user_ctl_val = 0x00000000,
> + .user_ctl_hi_val = 0x00000805,
> +};
> +
> +static struct clk_alpha_pll disp_cc_pll0 = {
> + .offset = 0x0,
> + .vco_table = lucid_evo_vco,
> + .num_vco = ARRAY_SIZE(lucid_evo_vco),
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
> + .clkr = {
> + .hw.init = &(const struct clk_init_data) {
> + .name = "disp_cc_pll0",
> + .parent_data = &(const struct clk_parent_data) {
> + .index = DT_BI_TCXO,
> + },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_lucid_evo_ops,
> + },
> + },
> +};
> +
> +/* 600.0 MHz Configuration */
> +static const struct alpha_pll_config disp_cc_pll1_config = {
Can disp_cc_pll0_config be used here?
> + .l = 0x1f,
> + .alpha = 0x4000,
> + .config_ctl_val = 0x20485699,
> + .config_ctl_hi_val = 0x00182261,
> + .config_ctl_hi1_val = 0x32aa299c,
> + .user_ctl_val = 0x00000000,
> + .user_ctl_hi_val = 0x00000805,
> +};
With that fixed:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
--
With best wishes
Dmitry
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