linux-kernel - RE: [PATCH v2 10/13] x86/irq: Extend checks for pending vectors to posted interrupts

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Message-ID: <BN9PR11MB5276129A5784849F2D06104D8C082@BN9PR11MB5276.namprd11.prod.outlook.com>
Date: Tue, 16 Apr 2024 03:47:48 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: Jacob Pan <jacob.jun.pan@...ux.intel.com>
CC: LKML <linux-kernel@...r.kernel.org>, X86 Kernel <x86@...nel.org>, "Peter
 Zijlstra" <peterz@...radead.org>, "iommu@...ts.linux.dev"
	<iommu@...ts.linux.dev>, Thomas Gleixner <tglx@...utronix.de>, Lu Baolu
	<baolu.lu@...ux.intel.com>, "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
	"Hansen, Dave" <dave.hansen@...el.com>, Joerg Roedel <joro@...tes.org>, "H.
 Peter Anvin" <hpa@...or.com>, Borislav Petkov <bp@...en8.de>, Ingo Molnar
	<mingo@...hat.com>, "Luse, Paul E" <paul.e.luse@...el.com>, "Williams, Dan J"
	<dan.j.williams@...el.com>, Jens Axboe <axboe@...nel.dk>, "Raj, Ashok"
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	<a.manzanares@...sung.com>, Bjorn Helgaas <helgaas@...nel.org>, "Zeng, Guang"
	<guang.zeng@...el.com>, "robert.hoo.linux@...il.com"
	<robert.hoo.linux@...il.com>
Subject: RE: [PATCH v2 10/13] x86/irq: Extend checks for pending vectors to
 posted interrupts

> From: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> Sent: Saturday, April 13, 2024 2:24 AM
> 
> Hi Kevin,
> 
> On Fri, 12 Apr 2024 09:25:57 +0000, "Tian, Kevin" <kevin.tian@...el.com>
> wrote:
> 
> > > From: Jacob Pan <jacob.jun.pan@...ux.intel.com>
> > > Sent: Saturday, April 6, 2024 6:31 AM
> > >
> > > During interrupt affinity change, it is possible to have interrupts
> > > delivered to the old CPU after the affinity has changed to the new one.
> > > To prevent lost interrupts, local APIC IRR is checked on the old CPU.
> > > Similar checks must be done for posted MSIs given the same reason.
> > >
> > > Consider the following scenario:
> > > 	Device		system agent		iommu
> > > 	memory CPU/LAPIC
> > > 1	FEEX_XXXX
> > > 2			Interrupt request
> > > 3						Fetch IRTE	->
> > > 4						->Atomic Swap
> > > PID.PIR(vec) Push to Global
> > > Observable(GO)
> > > 5						if (ON*)
> > > 	i						done;*
> >
> > there is a stray 'i'
> will fix, thanks
> 
> >
> > > 						else
> > > 6							send a
> > > notification ->
> > >
> > > * ON: outstanding notification, 1 will suppress new notifications
> > >
> > > If the affinity change happens between 3 and 5 in IOMMU, the old CPU's
> > > posted
> > > interrupt request (PIR) could have pending bit set for the vector being
> > > moved.
> >
> > how could affinity change be possible in 3/4 when the cache line is
> > locked by IOMMU? Strictly speaking it's about a change after 4 and
> > before 6.
> SW can still perform affinity change on IRTE and do the flushing on IR
> cache after IOMMU fectched it (step 3). They are async events.
> 
> In step 4, the atomic swap is on the PID cacheline, not IRTE.
> 

yeah, I mixed IRTE with PID.