linux-kernel - [PATCH 5/7] drm/msm/dpu: Correct dual-ctl -> dual-intf typo in comment

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Message-Id: <20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-5-78ae3ee9a697@somainline.org>
Date: Wed, 17 Apr 2024 01:57:45 +0200
From: Marijn Suijten <marijn.suijten@...ainline.org>
To: Rob Clark <robdclark@...il.com>, 
 Abhinav Kumar <quic_abhinavk@...cinc.com>, 
 Dmitry Baryshkov <dmitry.baryshkov@...aro.org>, Sean Paul <sean@...rly.run>, 
 David Airlie <airlied@...il.com>, Daniel Vetter <daniel@...ll.ch>, 
 Archit Taneja <architt@...eaurora.org>, 
 Chandan Uddaraju <chandanu@...eaurora.org>, Vinod Koul <vkoul@...nel.org>, 
 Sravanthi Kollukuduru <skolluku@...eaurora.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org, 
 freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org, 
 Jordan Crouse <jordan@...micpenguin.net>, 
 Rajesh Yadav <ryadav@...eaurora.org>, 
 Jeykumar Sankaran <jsanka@...eaurora.org>, 
 ~postmarketos/upstreaming@...ts.sr.ht, 
 AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, 
 Konrad Dybcio <konrad.dybcio@...aro.org>, 
 Martin Botka <martin.botka@...ainline.org>, 
 Jami Kettunen <jami.kettunen@...ainline.org>, 
 Marijn Suijten <marijn.suijten@...ainline.org>
Subject: [PATCH 5/7] drm/msm/dpu: Correct dual-ctl -> dual-intf typo in
 comment

This comment one line down references a single, "same CTL" that controls
two interfaces, so the comment should clearly describe two interfaces
used with a single active CTL and not "two CTLs".

Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Marijn Suijten <marijn.suijten@...ainline.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d9e7dbf0499c..7e849fe74801 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -428,7 +428,7 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
 	dpu_encoder_phys_vid_setup_timing_engine(phys_enc);
 
 	/*
-	 * For single flush cases (dual-ctl or pp-split), skip setting the
+	 * For single flush cases (dual-intf or pp-split), skip setting the
 	 * flush bit for the slave intf, since both intfs use same ctl
 	 * and HW will only flush the master.
 	 */

-- 
2.44.0