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Date: Tue, 16 Apr 2024 17:50:37 +0800
From: Chen Wang <unicornxw@...il.com>
To: adrian.hunter@...el.com,
aou@...s.berkeley.edu,
conor+dt@...nel.org,
guoren@...nel.org,
inochiama@...look.com,
jszhang@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
palmer@...belt.com,
paul.walmsley@...ive.com,
robh@...nel.org,
ulf.hansson@...aro.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
linux-mmc@...r.kernel.org,
linux-riscv@...ts.infradead.org,
chao.wei@...hgo.com,
haijiao.liu@...hgo.com,
xiaoguang.xing@...hgo.com,
tingzhu.wang@...hgo.com
Cc: Chen Wang <unicorn_wang@...look.com>
Subject: [PATCH 1/3] dt-bindings: mmc: sdhci-of-dwcmhsc: Add Sophgo SG2042 support
From: Chen Wang <unicorn_wang@...look.com>
SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers.
SG2042 defines 3 clocks for SD/eMMC controllers.
- AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc)
and blck(Core Base Clock in DWC_mshc), these 3 clocks share one
source, so reuse existing "core".
- 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse
existing "timer" which was added for rockchip specified.
- EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card".
Adding some examples.
Signed-off-by: Chen Wang <unicorn_wang@...look.com>
---
.../bindings/mmc/snps,dwcmshc-sdhci.yaml | 67 ++++++++++++++-----
1 file changed, 51 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
index 4d3031d9965f..a04ccae216cf 100644
--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml
@@ -21,6 +21,7 @@ properties:
- snps,dwcmshc-sdhci
- sophgo,cv1800b-dwcmshc
- sophgo,sg2002-dwcmshc
+ - sophgo,sg2042-dwcmshc
- thead,th1520-dwcmshc
reg:
@@ -30,23 +31,36 @@ properties:
maxItems: 1
clocks:
- minItems: 1
- items:
- - description: core clock
- - description: bus clock for optional
- - description: axi clock for rockchip specified
- - description: block clock for rockchip specified
- - description: timer clock for rockchip specified
-
+ anyOf:
+ - minItems: 1
+ items:
+ - description: core clock
+ - description: bus clock for optional
+ - description: axi clock for rockchip specified
+ - description: block clock for rockchip specified
+ - description: timer clock for rockchip specified
+
+ - minItems: 1
+ items:
+ - description: core clock
+ - description: timer clock
+ - description: card clock
clock-names:
- minItems: 1
- items:
- - const: core
- - const: bus
- - const: axi
- - const: block
- - const: timer
+ anyOf:
+ - minItems: 1
+ items:
+ - const: core
+ - const: bus
+ - const: axi
+ - const: block
+ - const: timer
+
+ - minItems: 1
+ items:
+ - const: core
+ - const: timer
+ - const: card
resets:
maxItems: 5
@@ -96,5 +110,26 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
};
-
+ - |
+ mmc@...000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xbb000 0x1000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>;
+ clock-names = "core";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - |
+ mmc@...000 {
+ compatible = "snps,dwcmshc-sdhci";
+ reg = <0xcc000 0x1000>;
+ interrupts = <0 25 0x4>;
+ clocks = <&cru 17>, <&cru 18>, <&cru 19>;
+ clock-names = "core", "timer", "card";
+ bus-width = <8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
...
--
2.25.1
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