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Message-ID: <fd7fe44ecbd99358bac583df3cc8192e250e758b.camel@linaro.org>
Date: Tue, 16 Apr 2024 13:21:15 +0100
From: André Draszik <andre.draszik@...aro.org>
To: Peter Griffin <peter.griffin@...aro.org>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org, 
 krzk+dt@...nel.org, conor+dt@...nel.org, vkoul@...nel.org,
 kishon@...nel.org,  alim.akhtar@...sung.com, avri.altman@....com,
 bvanassche@....org,  s.nawrocki@...sung.com, cw00.choi@...sung.com,
 jejb@...ux.ibm.com,  martin.petersen@...cle.com, chanho61.park@...sung.com,
 ebiggers@...nel.org,  linux-scsi@...r.kernel.org,
 linux-phy@...ts.infradead.org,  devicetree@...r.kernel.org,
 linux-clk@...r.kernel.org,  linux-samsung-soc@...r.kernel.org,
 linux-kernel@...r.kernel.org,  linux-arm-kernel@...ts.infradead.org,
 tudor.ambarus@...aro.org,  saravanak@...gle.com, willmcvicker@...gle.com
Subject: Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock
 controller

Hi Pete,

On Tue, 2024-04-16 at 12:56 +0100, Peter Griffin wrote:
> Hi André,
> 
> Thanks for the review.
> 
> On Fri, 5 Apr 2024 at 08:38, André Draszik <andre.draszik@...aro.org> wrote:
> > 
> > On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
> > > Enable the cmu_hsi2 clock management unit. It feeds some of
> > > the high speed interfaces such as PCIe and UFS.
> > > 
> > > Signed-off-by: Peter Griffin <peter.griffin@...aro.org>
> > > ---
> > >  arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> > >  1 file changed, 12 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > index eddb6b326fde..38ac4fb1397e 100644
> > > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > > @@ -1253,6 +1253,18 @@ pinctrl_hsi1: pinctrl@...40000 {
> > >                       interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
> > >               };
> > > 
> > > +             cmu_hsi2: clock-controller@...00000 {
> > > +                     compatible = "google,gs101-cmu-hsi2";
> > > +                     reg = <0x14400000 0x4000>;
> > > +                     #clock-cells = <1>;
> > > +                     clocks = <&ext_24_5m>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_BUS>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_PCIE>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
> > > +                              <&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
> > > +                     clock-names = "oscclk", "bus", "pcie", "ufs_embd", "mmc_card";
> > > +             };
> > 
> > This doesn't build because you didn't add the clock ids in the binding patch.
> 
> These clock IDs are for cmu_top, not cmu_hsi2.

Right. I replied to the wrong patch. Sorry for that. It is patch 7 that
uses clock ids that are only added in patch 8. The clock ids from patch 8
in include/dt-bindings/clock/google,gs101.h should be added in patch 1
instead.

Cheers,
Andre'

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