linux-kernel - Re: [PATCH 3/4] ARM: dts: BCM5301X: Add DT for ASUS RT-AC3200

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Date: Tue, 16 Apr 2024 20:15:07 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Arınç ÜNAL <arinc.unal@...nc9.com>,
 Krzysztof Kozlowski <krzk@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Florian Fainelli <f.fainelli@...il.com>,
 Hauke Mehrtens <hauke@...ke-m.de>, Rafal Milecki <zajec5@...il.com>,
 Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>
Cc: Tom Brautaset <tbrautaset@...il.com>, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 3/4] ARM: dts: BCM5301X: Add DT for ASUS RT-AC3200



On 4/15/2024 2:10 AM, Arınç ÜNAL wrote:
> On 15.04.2024 10:57, Krzysztof Kozlowski wrote:
>> On 14/04/2024 22:21, Arınç ÜNAL wrote:
>>> NVRAM is described as both flash device partition and memory mapped 
>>> NVMEM.
>>> This platform stores NVRAM on flash but makes it also memory accessible.
>>>
>>> As device partitions are described in board DTS, the nvram node must 
>>> also
>>
>> Sorry, but we do not talk about partitions. Partitions are indeed board
>> property. But the piece of hardware, so NVMEM, is provided by SoC.
>>
>>> be defined there as its address and size will be different by board. 
>>> It has
>>> been widely described on at least bcm4709 and bcm47094 SoC board DTS 
>>> files
>>> here.
>>
>> These not proper arguments. What you are saying here is that SoC does no
>> have nvram at address 0x1c08000. Instead you are saying there some sort
>> of bus going out of SoC to the board and on the board physically there
>> is some NVRAM sort of memory attached to this bus.
> 
> Yes that is the case. NVRAM is stored on a partition on the flash. On the
> Broadcom NorthStar platform, the NAND flash base is 0x1c000000, the NOR
> flash base is 0x1e000000.
> 
> For the board in this patch, the flash is a NAND flash. The NVRAM partition
> starts at address 0x00080000. Therefore, the NVRAM component's address is
> 0x1c080000.

Because the flash is memory mapped into the CPU's address space, a 
separate node was defined since it is not part of the "soc" node which 
describes the bridge that connects all of the peripherals.

Whether we should create an additional bus node which describes the 
bridge being used to access the flash devices using the MMIO windows is 
debatable. Rafal, what do you think?
-- 
Florian

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