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Message-ID: <c8e3f5d0-832b-4ab1-a65f-52f983ff110a@lunn.ch>
Date: Wed, 17 Apr 2024 20:39:54 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Oleksij Rempel <o.rempel@...gutronix.de>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
"David S. Miller" <davem@...emloft.net>,
Heiner Kallweit <hkallweit1@...il.com>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Woojung Huh <woojung.huh@...rochip.com>,
Arun Ramadoss <arun.ramadoss@...rochip.com>,
Richard Cochran <richardcochran@...il.com>,
Russell King <linux@...linux.org.uk>, kernel@...gutronix.de,
linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
UNGLinuxDriver@...rochip.com,
linux-stm32@...md-mailman.stormreply.com
Subject: Re: [PATCH net-next v1 2/4] net: phy: micrel: lan8841: set default
PTP latency values
On Wed, Apr 17, 2024 at 06:43:14PM +0200, Oleksij Rempel wrote:
> Set default PTP latency values to provide realistic path delay
> measurements and reflecting internal PHY latency asymetry.
>
> This values are based on ptp4l measurements for the path delay against
> identical PHY as link partner and latency asymmetry extracted from
> documented SOF Latency values of this PHY.
>
> Documented SOF Latency values are:
> TX 138ns/RX 430ns @ 1000Mbps
> TX 140ns/RX 615ns @ 100Mbps (fixed latency mode)
> TX 140ns/RX 488-524ns @ 100Mbps (variable latency mode)
> TX 654ns/227-2577ns @ 10Mbps
Does Half Duplex vs Full Duplex make a difference here?
> +static int lan8841_ptp_latency_init(struct phy_device *phydev)
> +{
> + int ret;
> +
> + ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_LATENCY_10M,
> + LAN8841_PTP_RX_LATENCY_10M_VAL);
> + if (ret)
> + return ret;
> +
> + ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_LATENCY_10M,
> + LAN8841_PTP_TX_LATENCY_10M_VAL);
> + if (ret)
> + return ret;
> +
> + ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_LATENCY_100M,
> + LAN8841_PTP_RX_LATENCY_100M_VAL);
> + if (ret)
> + return ret;
> +
> + ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_LATENCY_100M,
> + LAN8841_PTP_TX_LATENCY_100M_VAL);
> + if (ret)
> + return ret;
> +
> + ret = phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_RX_LATENCY_1000M,
> + LAN8841_PTP_RX_LATENCY_1000M_VAL);
> + if (ret)
> + return ret;
> +
> + return phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
> + LAN8841_PTP_TX_LATENCY_1000M,
> + LAN8841_PTP_TX_LATENCY_1000M_VAL);
> +}
What affect does this have on systems which have already applied
adjustments in user space to correct for this? Will this cause
regressions for such systems?
I know Richard has rejected changes like this in the past.
Andrew
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