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Message-ID: <37ffdb00-8d7a-4305-8814-6794c755c190@collabora.com>
Date: Wed, 17 Apr 2024 12:27:52 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Alexandre Mergnat <amergnat@...libre.com>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>, David Airlie <airlied@...il.com>,
Daniel Vetter <daniel@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>, Thomas Zimmermann <tzimmermann@...e.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, Matthias Brugger
<matthias.bgg@...il.com>, Jitao Shi <jitao.shi@...iatek.com>,
CK Hu <ck.hu@...iatek.com>, Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>, Michael Turquette
<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>
Cc: dri-devel@...ts.freedesktop.org, linux-mediatek@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-pwm@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 17/18] arm64: dts: mediatek: add display blocks support
for the MT8365 SoC
Il 16/04/24 17:53, Alexandre Mergnat ha scritto:
> - Add aliases for each display components to help display drivers.
> - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals
> for the LED driver of mobile LCM.
> - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane
> output)
> - Add the display mutex support.
> - Add the following display component support:
> - OVL0 (Overlay)
> - RDMA0 (Data Path Read DMA)
> - Color0
> - CCorr0 (Color Correction)
> - AAL0 (Adaptive Ambient Light)
> - GAMMA0
> - Dither0
> - DSI0 (Display Serial Interface)
> - RDMA1 (Data Path Read DMA)
> - DPI0 (Display Parallel Interface)
>
> Signed-off-by: Alexandre Mergnat <amergnat@...libre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++++++++++++++++
> 1 file changed, 146 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> index 24581f7410aa..a95f90da4491 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/clock/mediatek,mt8365-clk.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/memory/mediatek,mt8365-larb-port.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mediatek,mt8365-power.h>
>
> @@ -17,6 +18,19 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + aal0 = &aal0;
> + ccorr0 = &ccorr0;
> + color0 = &color0;
> + dither0 = &dither0;
> + dpi0 = &dpi0;
> + dsi0 = &dsi0;
> + gamma0 = &gamma0;
> + ovl0 = &ovl0;
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -607,6 +621,17 @@ spi: spi@...0a000 {
> status = "disabled";
> };
>
> + disp_pwm: pwm@...0e000 {
> + compatible = "mediatek,mt8365-disp-pwm",
> + "mediatek,mt8183-disp-pwm";
Fits in a single line
> + reg = <0 0x1100e000 0 0x1000>;
> + clock-names = "main", "mm";
> + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>,
> + <&infracfg CLK_IFR_DISP_PWM>;
same
> + power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
> + #pwm-cells = <2>;
> + };
> +
> i2c3: i2c@...0f000 {
> compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
> reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
> @@ -703,6 +728,15 @@ ethernet: ethernet@...a0000 {
> status = "disabled";
> };
>
> + mipi_tx0: dsi-phy@...00000 {
> + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11c00000 0 0x800>;
> + clock-output-names = "mipi_tx0_pll";
> + clocks = <&clk26m>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + };
> +
> u3phy: t-phy@...c0000 {
> compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
> #address-cells = <1>;
> @@ -732,6 +766,13 @@ mmsys: syscon@...00000 {
> #clock-cells = <1>;
> };
>
> + mutex: mutex@...01000 {
> + compatible = "mediatek,mt8365-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> + power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
> + };
> +
> smi_common: smi@...02000 {
> compatible = "mediatek,mt8365-smi-common";
> reg = <0 0x14002000 0 0x1000>;
> @@ -755,6 +796,111 @@ larb0: larb@...03000 {
> mediatek,larb-id = <0>;
> };
>
> + ovl0: ovl@...0b000 {
> + compatible = "mediatek,mt8365-disp-ovl",
> + "mediatek,mt8192-disp-ovl";
single line
> + reg = <0 0x1400b000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>;
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> + iommus = <&iommu M4U_PORT_DISP_OVL0>;
> + power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
> + };
> +
> + rdma0: rdma@...0d000 {
> + compatible = "mediatek,mt8365-disp-rdma",
> + "mediatek,mt8183-disp-rdma";
ditto
> + reg = <0 0x1400d000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>;
> + interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
> + iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> + mediatek,rdma-fifo-size = <5120>;
> + power-domains = <&spm MT8365_POWER_DOMAIN_MM>;
> + };
> +
> + color0: color@...0f000 {
> + compatible = "mediatek,mt8365-disp-color",
> + "mediatek,mt8173-disp-color";
..and all the others too (maybe not all, it's fine until 100 cols anyway)
Cheers,
Angelo
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