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Message-ID:
 <IA1PR20MB4953B3CD2B78DFC0A23F79B3BB0F2@IA1PR20MB4953.namprd20.prod.outlook.com>
Date: Wed, 17 Apr 2024 19:08:56 +0800
From: Inochi Amaoto <inochiama@...look.com>
To: Michael Turquette <mturquette@...libre.com>, 
	Stephen Boyd <sboyd@...nel.org>, Chen Wang <unicorn_wang@...look.com>, 
	Inochi Amaoto <inochiama@...look.com>, Arnd Bergmann <arnd@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	kernel test robot <lkp@...el.com>
Subject: Re: [PATCH] clk: sophgo: Use div64 for fpll rate calculation

On Sat, Apr 13, 2024 at 08:53:33AM GMT, Inochi Amaoto wrote:
> The CV1800 SoC needs to use 64-bit division for fpll rate
> calculation, which will cause problem on 32-bit system.
> Use div64 series function to avoid this problem.
> 
> Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
> Signed-off-by: Inochi Amaoto <inochiama@...look.com>
> Reported-by: kernel test robot <lkp@...el.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/

Close this patch as favor the patch from Arnd, which is simpler.
https://lore.kernel.org/all/20240415134532.3467817-1-arnd@kernel.org/

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