linux-kernel - Re: [PATCH 4/5] arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <999116f9-47f8-b307-1251-06c26b7c3138@quicinc.com>
Date: Wed, 17 Apr 2024 17:22:10 +0530
From: Sibi Sankar <quic_sibis@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: <sudeep.holla@....com>, <cristian.marussi@....com>, <andersson@...nel.org>,
        <konrad.dybcio@...aro.org>, <jassisinghbrar@...il.com>,
        <robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
        <linux-kernel@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <quic_rgottimu@...cinc.com>,
        <quic_kshivnan@...cinc.com>, <conor+dt@...nel.org>,
        <quic_gkohli@...cinc.com>, <quic_nkela@...cinc.com>,
        <quic_psodagud@...cinc.com>
Subject: Re: [PATCH 4/5] arm64: dts: qcom: x1e80100: Add cpucp mailbox and
 sram nodes



On 4/16/24 22:00, Dmitry Baryshkov wrote:
> On Thu, 28 Mar 2024 at 11:52, Sibi Sankar <quic_sibis@...cinc.com> wrote:
>>
>> Add the cpucp mailbox and sram nodes required by SCMI perf protocol
>> on X1E80100 SoCs.
>>
>> Signed-off-by: Sibi Sankar <quic_sibis@...cinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/x1e80100.dtsi | 26 ++++++++++++++++++++++++++
>>   1 file changed, 26 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> index 28f65296781d..4e0ec859ed61 100644
>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
>> @@ -4974,6 +4974,13 @@ gic_its: msi-controller@...40000 {
>>                          };
>>                  };
>>
>> +               cpucp_mbox: mailbox@...30000 {
>> +                       compatible = "qcom,x1e80100-cpucp-mbox";
>> +                       reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
>> +                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> +                       #mbox-cells = <1>;
>> +               };
>> +
>>                  apps_rsc: rsc@...00000 {
>>                          compatible = "qcom,rpmh-rsc";
>>                          reg = <0 0x17500000 0 0x10000>,
>> @@ -5157,6 +5164,25 @@ frame@...0d000 {
>>                          };
>>                  };
>>
>> +               sram: sram@...4e000 {
>> +                       compatible = "mmio-sram";
>> +                       reg = <0x0 0x18b4e000 0x0 0x400>;
>> +                       ranges = <0x0 0x0 0x18b4e000 0x400>;
>> +
>> +                       #address-cells = <1>;
>> +                       #size-cells = <1>;
>> +
>> +                       cpu_scp_lpri0: scmi-shmem@0 {
> 
> This doesn't seem to follow the schema.

ack, will rename the nodes in the next re-spin.

-Sibi

> 
>> +                               compatible = "arm,scmi-shmem";
>> +                               reg = <0x0 0x200>;
>> +                       };
>> +
>> +                       cpu_scp_lpri1: scmi-shmem@200 {
>> +                               compatible = "arm,scmi-shmem";
>> +                               reg = <0x200 0x200>;
>> +                       };
>> +               };
>> +
>>                  system-cache-controller@...00000 {
>>                          compatible = "qcom,x1e80100-llcc";
>>                          reg = <0 0x25000000 0 0x200000>,
>> --
>> 2.34.1
>>
>>
> 
>