linux-kernel - Re: [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e938c677de8e8c8742701c7660b84706.sboyd@kernel.org>
Date: Fri, 19 Apr 2024 15:22:01 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Alexandru Gagniuc <mr.nuke.me@...il.com>, Bjorn Andersson <andersson@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>, Conor Dooley <conor+dt@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, Konrad Dybcio <konrad.dybcio@...aro.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Krzysztof Wilczyński <kw@...ux.com>, Lorenzo Pieralisi <lpieralisi@...nel.org>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>, Michael Turquette <mturquette@...libre.com>, Rob Herring <robh@...nel.org>, Vinod Koul <vkoul@...nel.org>, devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org, linux-phy@...ts.infradead.org
Cc: Alexandru Gagniuc <mr.nuke.me@...il.com>
Subject: Re: [PATCH v3 2/7] clk: qcom: gcc-ipq9574: Add PCIe pipe clocks

Quoting Alexandru Gagniuc (2024-04-15 11:20:47)
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> index 0a3f846695b8..c748d2f124f3 100644
> --- a/drivers/clk/qcom/gcc-ipq9574.c
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -1569,6 +1569,24 @@ static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {
>         },
>  };
>  
> +static struct clk_branch gcc_pcie0_pipe_clk = {
> +       .halt_reg = 0x28044,
> +       .halt_check = BRANCH_HALT_DELAY,
> +       .clkr = {
> +               .enable_reg = 0x28044,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){
> +                       .name = "gcc_pcie0_pipe_clk",
> +                       .parent_hws = (const struct clk_hw *[]) {
> +                               &pcie0_pipe_clk_src.clkr.hw
> +                       },
> +                       .num_parents = 1,
> +                       .flags = CLK_SET_RATE_PARENT,
> +                       .ops = &clk_branch2_ops,
> +               },
> +       },
> +};
> +
>  static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
>         .reg = 0x29064,
>         .clkr = {
> @@ -1583,6 +1601,24 @@ static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {
>         },
>  };
>  
> +static struct clk_branch gcc_pcie1_pipe_clk = {
> +       .halt_reg = 0x29044,
> +       .halt_check = BRANCH_HALT_DELAY,
> +       .clkr = {
> +               .enable_reg = 0x29044,
> +               .enable_mask = BIT(0),
> +               .hw.init = &(struct clk_init_data){

const clk_init_data please.