linux-kernel - Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

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Message-ID: <CAMuHMdWCHD+AuP9v2fBygDv-fJqP4RZ=Gtp3PX9b1K-GX1+XQg@mail.gmail.com>
Date: Fri, 19 Apr 2024 09:44:25 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Thomas Gleixner <tglx@...utronix.de>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, linux-renesas-soc@...r.kernel.org, 
	linux-riscv@...ts.infradead.org, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

Hi Prabhakar,

On Fri, Apr 19, 2024 at 9:15 AM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
> On Thu, Apr 18, 2024 at 4:11 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Wed, Apr 3, 2024 at 10:36 PM Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared
> > > to the RZ/G2L (family) SoC.
> > >
> > > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC
> > > controller driver. Two new registers, IMSK and TMSK, are defined to
> > > handle masking on RZ/Five SoC. The implementation utilizes a new data
> > > structure, `struct rzg2l_irqc_data`, to determine mask support for a
> > > specific controller instance.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > ---
> > > v1->v2
> > > - Added IRQCHIP_MATCH() for RZ/Five
> > > - Retaining a copy of OF data in priv
> > > - Rebased the changes
> >
> > Thanks for the update!
> >
> > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > >         u32     titsr[2];
> > >  };
> > >
> > > +/**
> > > + * struct rzg2l_irqc_of_data - OF data structure
> > > + * @mask_supported: Indicates if mask registers are available
> > > + */
> > > +struct rzg2l_irqc_of_data {
> > > +       bool    mask_supported;
> > > +};
> > > +
> > >  /**
> > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > >   * @base:      Controller's base address
> > > + * @data:      OF data pointer
> > >   * @fwspec:    IRQ firmware specific data
> > >   * @lock:      Lock to serialize access to hardware registers
> > >   * @cache:     Registers cache for suspend/resume
> > >   */
> > >  static struct rzg2l_irqc_priv {
> > >         void __iomem                    *base;
> > > +       const struct rzg2l_irqc_of_data *data;
> >
> > That's not a copy, but a pointer.
> >
> Oops, should that be OK or shall I create a copy instead?

If you would use a copy, all SoC-specific rzg2l_irqc_of_data structures
could become __initconst.

However, depending on how far you want to go with the irq_chip
separation, you may no longer need this field anyway.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68korg

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds