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Message-ID: <20240419114633.GB7195@thinkpad>
Date: Fri, 19 Apr 2024 17:16:33 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Frank Li <Frank.Li@....com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>, Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Conor Dooley <conor+dt@...nel.org>, imx@...ts.linux.dev,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v8 5/5] PCI: dwc: Add generic MSG TLP support for sending
PME_Turn_Off when system suspend
On Thu, Apr 18, 2024 at 12:04:28PM -0400, Frank Li wrote:
> Instead of relying on the vendor specific implementations to send the
> PME_Turn_Off message, let's introduce a generic way of sending the message
> using the MSG TLP.
>
> This is achieved by reserving a region for MSG TLP of size
> 'pci->region_align', at the end of the first IORESOURCE_MEM window of the
> host bridge. And then sending the PME_Turn_Off message during system
> suspend with the help of iATU.
>
> The reason for reserving the MSG TLP region at the end of the
> IORESOURCE_MEM is to avoid generating holes in between. Because, when the
> region is allocated using allocate_resource(), memory will be allocated
> from the start of the window. Later, if memory gets allocated for an
> endpoint of size bigger than 'region_align', there will be a hole between
> MSG TLP region and endpoint memory.
>
> It should be noted that this generic implementation is optional for the
> glue drivers and can be overridden by a custom 'pme_turn_off' callback.
>
> Signed-off-by: Frank Li <Frank.Li@....com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
- Mani
> ---
> drivers/pci/controller/dwc/pcie-designware-host.c | 95 +++++++++++++++++++++--
> drivers/pci/controller/dwc/pcie-designware.h | 3 +
> 2 files changed, 93 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 3a9cb4be22ab2..a0822d5371bc5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -398,6 +398,32 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp)
> return 0;
> }
>
> +static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct resource_entry *win;
> + struct resource *res;
> +
> + win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM);
> + if (win) {
> + res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL);
> + if (!res)
> + return;
> +
> + /*
> + * Allocate MSG TLP region of size 'region_align' at the end of
> + * the host bridge window.
> + */
> + res->start = win->res->end - pci->region_align + 1;
> + res->end = win->res->end;
> + res->name = "msg";
> + res->flags = win->res->flags | IORESOURCE_BUSY;
> +
> + if (!devm_request_resource(pci->dev, win->res, res))
> + pp->msg_res = res;
> + }
> +}
> +
> int dw_pcie_host_init(struct dw_pcie_rp *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> @@ -484,6 +510,18 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>
> dw_pcie_iatu_detect(pci);
>
> + /*
> + * Allocate the resource for MSG TLP before programming the iATU
> + * outbound window in dw_pcie_setup_rc(). Since the allocation depends
> + * on the value of 'region_align', this has to be done after
> + * dw_pcie_iatu_detect().
> + *
> + * Glue drivers need to set 'use_atu_msg' before dw_pcie_host_init() to
> + * make use of the generic MSG TLP implementation.
> + */
> + if (pp->use_atu_msg)
> + dw_pcie_host_request_msg_tlp_res(pp);
> +
> ret = dw_pcie_edma_detect(pci);
> if (ret)
> goto err_free_msi;
> @@ -700,7 +738,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> atu.type = PCIE_ATU_TYPE_MEM;
> atu.cpu_addr = entry->res->start;
> atu.pci_addr = entry->res->start - entry->offset;
> - atu.size = resource_size(entry->res);
> +
> + /* Adjust iATU size if MSG TLP region was allocated before */
> + if (pp->msg_res && pp->msg_res->parent == entry->res)
> + atu.size = resource_size(entry->res) -
> + resource_size(pp->msg_res);
> + else
> + atu.size = resource_size(entry->res);
>
> ret = dw_pcie_prog_outbound_atu(pci, &atu);
> if (ret) {
> @@ -733,6 +777,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
> dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
> pci->num_ob_windows);
>
> + pp->msg_atu_index = i;
> +
> i = 0;
> resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
> if (resource_type(entry->res) != IORESOURCE_MEM)
> @@ -838,11 +884,47 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
> }
> EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
>
> +static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
> +{
> + struct dw_pcie_ob_atu_cfg atu = { 0 };
> + void __iomem *mem;
> + int ret;
> +
> + if (pci->num_ob_windows <= pci->pp.msg_atu_index)
> + return -ENOSPC;
> +
> + if (!pci->pp.msg_res)
> + return -ENOSPC;
> +
> + atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
> + atu.routing = PCIE_MSG_TYPE_R_BC;
> + atu.type = PCIE_ATU_TYPE_MSG;
> + atu.size = resource_size(pci->pp.msg_res);
> + atu.index = pci->pp.msg_atu_index;
> +
> + atu.cpu_addr = pci->pp.msg_res->start;
> +
> + ret = dw_pcie_prog_outbound_atu(pci, &atu);
> + if (ret)
> + return ret;
> +
> + mem = ioremap(atu.cpu_addr, pci->region_align);
> + if (!mem)
> + return -ENOMEM;
> +
> + /* A dummy write is converted to a Msg TLP */
> + writel(0, mem);
> +
> + iounmap(mem);
> +
> + return 0;
> +}
> +
> int dw_pcie_suspend_noirq(struct dw_pcie *pci)
> {
> u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> u32 val;
> - int ret;
> + int ret = 0;
>
> /*
> * If L1SS is supported, then do not put the link into L2 as some
> @@ -854,10 +936,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
> if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT)
> return 0;
>
> - if (!pci->pp.ops->pme_turn_off)
> - return 0;
> + if (pci->pp.ops->pme_turn_off)
> + pci->pp.ops->pme_turn_off(&pci->pp);
> + else
> + ret = dw_pcie_pme_turn_off(pci);
>
> - pci->pp.ops->pme_turn_off(&pci->pp);
> + if (ret)
> + return ret;
>
> ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE,
> PCIE_PME_TO_L2_TIMEOUT_US/10,
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 703b50bc5e0f1..dca5de4c6e877 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -341,6 +341,9 @@ struct dw_pcie_rp {
> struct pci_host_bridge *bridge;
> raw_spinlock_t lock;
> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> + bool use_atu_msg;
> + int msg_atu_index;
> + struct resource *msg_res;
> };
>
> struct dw_pcie_ep_ops {
>
> --
> 2.34.1
>
--
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