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Message-ID: <b0a202f1-212e-4846-b472-1f1d1a3314cf@linux.intel.com>
Date: Fri, 19 Apr 2024 09:57:54 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Zhang Rui <rui.zhang@...el.com>, peterz@...radead.org
Cc: mingo@...hat.com, tglx@...utronix.de, bp@...en8.de,
dave.hansen@...ux.intel.com, x86@...nel.org,
linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
ak@...ux.intel.com
Subject: Re: [PATCH 1/3] perf/x86/intel/cstate: Fix
Alderlake/Raptorlake/Meteorlake
On 2024-04-19 3:10 a.m., Zhang Rui wrote:
> The spec changes after the patch submitted and PC7/PC9 are removed from
> Alderlake and later client platforms.
>
> Remove PC7/PC9 support in cstate PMU.
>
> Fixes: d0ca946bcf84 ("perf/x86/cstate: Add Alder Lake CPU support")
> Signed-off-by: Zhang Rui <rui.zhang@...el.com>
The series looks good to me.
Reviewed-by: Kan Liang <kan.liang@...ux.intel.com>
Thanks,
Kan
> ---
> arch/x86/events/intel/cstate.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
> index 326c8cd5aa2d..b304430ba64a 100644
> --- a/arch/x86/events/intel/cstate.c
> +++ b/arch/x86/events/intel/cstate.c
> @@ -81,7 +81,7 @@
> * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter.
> * perf code: 0x03
> * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL,
> - * KBL,CML,ICL,TGL,RKL,ADL,RPL,MTL
> + * KBL,CML,ICL,TGL,RKL
> * Scope: Package (physical package)
> * MSR_PKG_C8_RESIDENCY: Package C8 Residency Counter.
> * perf code: 0x04
> @@ -90,8 +90,7 @@
> * Scope: Package (physical package)
> * MSR_PKG_C9_RESIDENCY: Package C9 Residency Counter.
> * perf code: 0x05
> - * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL,
> - * ADL,RPL,MTL
> + * Available model: HSW ULT,KBL,CNL,CML,ICL,TGL,RKL
> * Scope: Package (physical package)
> * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.
> * perf code: 0x06
> @@ -642,9 +641,7 @@ static const struct cstate_model adl_cstates __initconst = {
> .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
> BIT(PERF_CSTATE_PKG_C3_RES) |
> BIT(PERF_CSTATE_PKG_C6_RES) |
> - BIT(PERF_CSTATE_PKG_C7_RES) |
> BIT(PERF_CSTATE_PKG_C8_RES) |
> - BIT(PERF_CSTATE_PKG_C9_RES) |
> BIT(PERF_CSTATE_PKG_C10_RES),
> };
>
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